Ramesh Karri

	2009
86		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Logic Mapping in Crossbar-Based Nanoarchitectures. IEEE Design & Test of Computers 26(1): 68-77 (2009)
	2007
85		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. DATE 2007: 865-869
84		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. DSN 2007: 216-224
83		Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri: Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. FDTC 2007: 112-119
82		Kyosun Kim, Kaijie Wu, Ramesh Karri: The Robust QCA Adder Designs Using Composable QCA Building Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 176-183 (2007)
81		Bo Yang, Ramesh Karri: Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1763-1769 (2007)
80		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Towards Nanoelectronics Processor Architectures. J. Electronic Testing 23(2-3): 235-254 (2007)
	2006
79		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Topology aware mapping of logic functions onto nanowire-based crossbar architectures. DAC 2006: 723-726
78		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. European Test Symposium 2006: 63-68
77		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. VTS 2006: 214-221
76		Bo Yang, Ramesh Karri, David A. McGrew: A High-Speed Hardware Architecture for Universal Message Authentication Code. IEEE Journal on Selected Areas in Communications 24(10): 1831-1839 (2006)
75		Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri: Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. IEEE Trans. Computers 55(10): 1230-1239 (2006)
74		Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 19-30 (2006)
73		Bo Yang, Kaijie Wu, Ramesh Karri: Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2287-2293 (2006)
72		Kaijie Wu, Ramesh Karri: Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 413-422 (2006)
71		Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri: Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1163-1169 (2006)
70		Kyosun Kim, Kaijie Wu, Ramesh Karri: Quantum-Dot Cellular Automata Design Guideline. IEICE Transactions 89-A(6): 1607-1614 (2006)
	2005
69		Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu: Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195
68		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault tolerant nanoelectronic processor architectures. ASP-DAC 2005: 311-316
67		Bo Yang, Ramesh Karri: Power optimization for universal hash function data path using divide-and-concatenate technique. CODES+ISSS 2005: 219-224
66		Bo Yang, Kaijie Wu, Ramesh Karri: Secure scan: a design-for-test architecture for crypto chips. DAC 2005: 135-140
65		Kyosun Kim, Kaijie Wu, Ramesh Karri: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. DATE 2005: 1214-1219
64		Bo Yang, Nikhil Joshi, Ramesh Karri: A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). FPGA 2005: 280
63		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. ICCD 2005: 533-542
62		Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel: On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. IOLTS 2005: 141-146
61		Bo Yang, Ramesh Karri, David A. McGrew: Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1740-1747 (2005)
	2004
60		Nikhil Joshi, Kaijie Wu, Ramesh Karri: Concurrent Error Detection Schemes for Involution Ciphers. CHES 2004: 400-412
59		Bo Yang, Ramesh Karri, David A. McGrew: Divide-and-concatenate: an architecture level optimization technique for universal hash functions. DAC 2004: 614-617
58		Bo Yang, Ramesh Karri, David A. McGrew: Divide and concatenate: a scalable hardware architecture for universal MAC. FPGA 2004: 258
57		Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. ITC 2004: 1242-1248
56		Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. ITC 2004: 339-344
55		Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. ITC 2004: 472-478
54		Kaijie Wu, Ramesh Karri: Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1476-1485 (2004)
53		Inki Hong, Miodrag Potkonjak, Ramesh Karri: A heterogeneous built-in self-repair approach using system-level synthesis flexibility. IEEE Transactions on Reliability 53(1): 93-101 (2004)
52		Darshan Sonecha, Bo Yang, Ramesh Karri, David A. McGrew: High speed architectures for Leviathan: a binary tree based stream cipher. Microprocessors and Microsystems 28(10): 573-584 (2004)
	2003
51		Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers. CHES 2003: 113-124
50		Kaijie Wu, Ramesh Karri: Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ITC 2003: 902-911
49		Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Parity-Based Concurrent Error Detection in Symmetric Block Ciphers. ITC 2003: 919-926
48		Ramesh Karri, Piyush Mishra: Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. PATMOS 2003: 358-368
47		Kaijie Wu, Ramesh Karri: Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. IEEE Transactions on Reliability 52(4): 501-511 (2003)
46		Ramesh Karri, Piyush Mishra: Optimizing the Energy Consumed by Secure Wireless Sessions - Wireless Transport Layer Security Case Study. MONET 8(2): 177-185 (2003)
45		Kaijie Wu, Piyush Mishra, Ramesh Karri: Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. Microelectronics Journal 34(1): 31-39 (2003)
	2002
44		Kaijie Wu, Ramesh Karri: Exploiting Idle Cycles for Algorithm Level Re-Computing. DATE 2002: 842-846
43		Ramesh Karri, Kaijie Wu: Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. IEEE Trans. VLSI Syst. 10(6): 864-875 (2002)
42		Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1509-1517 (2002)
41		Ramesh Karri, Balakrishnan Iyer, Israel Koren: Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 877-888 (2002)
40		Kaijie Wu, Ramesh Karri: Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1077-1087 (2002)
	2001
39		Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. DAC 2001: 579-585
38		Kaijie Wu, Ramesh Karri: Idle Cycles Based Concurrent Error Detection of RC6 Encryption. DFT 2001: 200-205
37		Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435
36		Kaijie Wu, Ramesh Karri: Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ICCAD 2001: 537-
35		Kaijie Wu, Ramesh Karri: Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ITC 2001: 221-229
34		Ramesh Karri, Balakrishnan Iyer: Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. ACM Trans. Design Autom. Electr. Syst. 6(4): 505-515 (2001)
33		Ramesh Karri: Guest editor's introduction to special section on high-level design validation and test. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 353-354 (2001)
	2000
32		Ramesh Karri, Kaijie Wu: Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ITC 2000: 971-978
31		Ramesh Karri, Kyosun Kim, Miodrag Potkonjak: Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors. IEEE Trans. Computers 49(11): 1272-1284 (2000)
	1999
30		Inki Hong, Miodrag Potkonjak, Ramesh Karri: Power optimization using divide-and-conquer techniques for minimization of the number of operations. ACM Trans. Design Autom. Electr. Syst. 4(4): 405-429 (1999)
	1998
29		Inki Hong, Miodrag Potkonjak, Ramesh Karri: Heterogeneous BISR-approach using System Level Synthesis Flexibility. ASP-DAC 1998: 289-294
28		Ramesh Karri, Nilanjan Mukherjee: Versatile BIST: an integrated approach to on-line/off-line BIST. ITC 1998: 910-917
27		Ramesh Karri, Michael Nicolaidis: Guest Editors' Introduction: Online VLSI Testing. IEEE Design & Test of Computers 15(4): 12-16 (1998)
26		Aurobindo Dasgupta, Ramesh Karri: High-reliability, low-energy microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1273-1280 (1998)
25		Nilanjan Mukherjee, Ramesh Karri: Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. J. Electronic Testing 13(2): 189-200 (1998)
	1997
24		Miodrag Potkonjak, Kyosun Kim, Ramesh Karri: Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. DAC 1997: 252-257
23		Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Synthesis of Application Specific Programmable Processors. DAC 1997: 353-358
22		Inki Hong, Miodrag Potkonjak, Ramesh Karri: Power optimization using divide-and-conquer techniques for minimization of the number of operations. ICCAD 1997: 108-111
21		Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. ICCAD 1997: 33-38
20		Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, S. Roy, S. Wu: A Parameterized VHDL Library for On-Line Testing. ITC 1997: 479-488
	1996
19		Balakrishnan Iyer, Ramesh Karri: Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. DAC 1996: 137-142
18		Aurobindo Dasgupta, Ramesh Karri: Electromigration Reliability Enhancement via Bus Activity Distribution. DAC 1996: 353-356
17		Aurobindo Dasgupta, Ramesh Karri: Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. DAC 1996: 819-824
16		Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Heterogeneous built-in resiliency of application specific programmable processors. ICCAD 1996: 406-411
15		Ramesh Karri, Karin Högstedt, Alex Orailoglu: Computer-Aided Design of Fault-Tolerant VLSI Systems. IEEE Design & Test of Computers 13(3): 88-96 (1996)
14		Alex Orailoglu, Ramesh Karri: Automatic Synthesis of Self-Recovering VLSI Systems. IEEE Trans. Computers 45(2): 131-142 (1996)
	1995
13		Balakrishnan Iyer, Ramesh Karri, Israel Koren: Phantom redundancy: a high-level synthesis approach for manufacturability. ICCAD 1995: 658-661
12		Aurobindo Dasgupta, Ramesh Karri: Synthesis of Reliable Application Specific Heterogeneous Multiprocessors. ISCAS 1995: 1215-1218
11		Aurobindo Dasgupta, Ramesh Karri: Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. ISLPD 1995: 69-74
	1994
10		Ramesh Karri, Alex Orailoglu: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. DAC 1994: 552-556
9		Sergei Sokolov, Ramesh Karri: Allocation and Binding During Fault-Secure Microarchitecture Synthesis. ICCD 1994: 327-330
8		Alex Orailoglu, Ramesh Karri: Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. IEEE Trans. VLSI Syst. 2(3): 304-311 (1994)
7		Alex Orailoglu, Ramesh Karri: Synthesis of fault-tolerant and real-time microarchitectures. Journal of Systems and Software 25(1): 73-84 (1994)
	1993
6		Ramesh Karri, Alex Orailoglu: High-Level Synthesis of Fault-Secure Microarchitectures. DAC 1993: 429-433
5		Ramesh Karri, Alex Orailoglu: Optimal Self-Recovering Microarchitecture Synthesis. FTCS 1993: 512-521
	1992
4		Ramesh Karri, Alex Orailoglu: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. DAC 1992: 662-665
3		Ramesh Karri, Alex Orailoglu: Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. FTCS 1992: 519-526
2		Alex Orailoglu, Ramesh Karri: High-Level Synthesis of Self-Recovering MicroArchitectures. ICCD 1992: 286-289
	1991
1		Ramesh Karri, Alex Orailoglu: ALPS: An Algorithm for Pipeline Data Path Synthesis. MICRO 1991: 124-132

Coauthor Index

1	Aurobindo Dasgupta	[11] [12] [17] [18] [26]
2	M. Ding	[20]
3	Michael Gössel	[49] [51] [57] [62]
4	Karin Högstedt	[15]
5	Inki Hong	[22] [29] [30] [53]
6	Balakrishnan Iyer	[13] [19] [34] [41]
7	Nikhil Joshi	[60] [64] [71] [75] [83]
8	I. Kim	[20]
9	Kyosun Kim	[16] [21] [23] [24] [31] [65] [70] [74] [82]
10	Yongkook Kim	[37] [39] [42]
11	Israel Koren	[13] [41]
12	G. Kouznetsov	[62]
13	Grigori Kuznetsov	[49] [51] [57]
14	David A. McGrew	[52] [58] [59] [61] [76]
15	Piyush Mishra	[37] [39] [42] [45] [46] [48]
16	Nilanjan Mukherjee	[25] [28]
17	Michael Nicolaidis	[27]
18	Vitalij Ocheretnij	[62]
19	Alex Orailoglu	[1] [2] [3] [4] [5] [6] [7] [8] [10] [14] [15] [55] [63] [68] [69] [77] [78] [79] [80] [84] [85] [86]
20	Miodrag Potkonjak	[16] [21] [22] [23] [24] [29] [30] [31] [53] [74]
21	Wenjing Rao	[55] [63] [68] [77] [78] [79] [80] [84] [85] [86]
22	S. Roy	[20]
23	S. Seshadri	[20]
24	Sergei Sokolov	[9]
25	Darshan Sonecha	[52]
26	Richard Stern	[83]
27	Charles E. Stroud	[20]
28	Jayachandran Sundararajan	[71] [75]
29	Tongquan Wei	[69]
30	Kaijie Wu	[32] [35] [36] [37] [38] [39] [40] [42] [43] [44] [45] [47] [50] [54] [56] [57] [60] [65] [66] [69] [70] [71] [72] [73] [75] [82] [83]
31	S. Wu	[20]
32	Bo Yang	[52] [56] [58] [59] [61] [64] [66] [67] [73] [75] [76] [81]

Colors in the list of coauthors