| 2009 | ||
|---|---|---|
| 69 | Junguk Cho, Bridget Benson, Shahnam Mirzaei, Ryan Kastner: Parallelized Architecture of Multiple Classifiers for Face Detection. ASAP 2009: 75-82 | |
| 68 | Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner: Xquasher: a tool for efficient computation of multiple linear expressions. DAC 2009: 254-257 | |
| 67 | Ying Li, Bridget Benson, Ryan Kastner, Xing Zhang: Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK. ERSA 2009: 136-142 | |
| 66 | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner: Fpga-based face detection system using Haar classifiers. FPGA 2009: 103-112 | |
| 65 | Bridget Benson, Ali Irturk, Junguk Cho, Ryan Kastner: Energy benefits of reconfigurable hardware for use in underwater snesor nets. IPDPS 2009: 1-7 | |
| 64 | Junguk Cho, Bridget Benson, Ryan Kastner: Hardware acceleration of multi-view face detection. SASP 2009: 66-69 | |
| 2008 | ||
| 63 | Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals, Richard E. Cagley: Design space exploration of a cooperative MIMO receiver for reconfigurable architectures. ASAP 2008: 167-172 | |
| 62 | Ryan Kastner, Ted Huffmire: Threats and Challenges in Reconfigurable Hardware Security. ERSA 2008: 334-345 | |
| 61 | Ted Huffmire, Jonathan Valamehr, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine: Trustworthy System Security through 3-D Integrated Hardware. HOST 2008: 91-92 | |
| 60 | Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan Kastner: An FPGA Design Space Exploration Tool for Matrix Inversion Architectures. SASP 2008: 42-47 | |
| 59 | Bridget Benson, Ali Irturk, Junguk Cho, Ryan Kastner: Survey of hardware platforms for an energy efficient implementation of matching pursuits algorithm for shallow water networks. Underwater Networks 2008: 83-86 | |
| 58 | Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood: Designing secure systems on reconfigurable hardware. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) | |
| 57 | Ted Huffmire, Timothy Sherwood, Ryan Kastner, Timothy E. Levin: Enforcing memory policy specifications in reconfigurable hardware. Computers & Security 27(5-6): 197-215 (2008) | |
| 56 | Ted Huffmire, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine: Managing Security in FPGA-Based Embedded Systems. IEEE Design & Test of Computers 25(6): 590-598 (2008) | |
| 2007 | ||
| 55 | Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong: Combining static and dynamic defect-tolerance techniques for nanoscale memory systems. ICCAD 2007: 773-778 | |
| 54 | Ted Huffmire, Brett Brotherton, Gang Wang, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine: Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems. IEEE Symposium on Security and Privacy 2007: 281-295 | |
| 53 | Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner: Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) | |
| 52 | Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner: Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1010-1029 (2007) | |
| 51 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Algebraic Methods for Optimizing Constant Multiplications in Linear Systems. VLSI Signal Processing 49(1): 31-50 (2007) | |
| 2006 | ||
| 50 | Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner: Design space exploration using time and resource duality with the ant colony optimization. DAC 2006: 451-454 | |
| 49 | Yan Meng, Timothy Sherwood, Ryan Kastner: Leakage power reduction of embedded memories on FPGAs through location assignment. DAC 2006: 612-617 | |
| 48 | Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh: Layout driven data communication optimization for high level synthesis. DATE 2006: 1185-1190 | |
| 47 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Optimizing high speed arithmetic circuits using three-term extraction. DATE 2006: 1294-1299 | |
| 46 | Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ryan Kastner: Policy-Driven Memory Protection for Reconfigurable Hardware. ESORICS 2006: 461-478 | |
| 45 | Gang Wang, Wenrui Gong, Ryan Kastner: Defect-Tolerant Nanocomputing Using Bloom Filters. FCCM 2006: 277-278 | |
| 44 | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner: High speed FIR filter implementation using add and shift method. FPGA 2006: 231 | |
| 43 | Ronald A. Iltis, Shahnam Mirzaei, Ryan Kastner, Richard E. Cagley, Brad T. Weals: Carrier Offset and Channel Estimation for Cooperative MIMO Sensor Networks. GLOBECOM 2006 | |
| 42 | Gang Wang, Wenrui Gong, Ryan Kastner: On the use of Bloom filters for defect maps in nanocomputing. ICCAD 2006: 743-746 | |
| 41 | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner: FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. ICCD 2006 | |
| 40 | Bridget Benson, Grace Chang, Derek Manov, Brian Graham, Ryan Kastner: Design of a low-cost acoustic modem for moored oceanographic applications. Underwater Networks 2006: 71-78 | |
| 39 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2012-2022 (2006) | |
| 38 | Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006) | |
| 37 | Gang Wang, Wenrui Gong, Ryan Kastner: Application partitioning on programmable platforms using the ant colony optimization. J. Embedded Computing 2(1): 119-136 (2006) | |
| 2005 | ||
| 36 | Gang Wang, Wenrui Gong, Ryan Kastner: Instruction scheduling using MAX-MIN ant system optimization. ACM Great Lakes Symposium on VLSI 2005: 44-49 | |
| 35 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions. ASP-DAC 2005: 523-528 | |
| 34 | Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner: MP core: algorithm and design techniques for efficient channel estimation in wireless applications. DAC 2005: 297-302 | |
| 33 | Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood: Data Partitioning and Optimizations for Reconfigurable Architectures. ERSA 2005: 239-242 | |
| 32 | Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29 | |
| 31 | Yan Meng, Timothy Sherwood, Ryan Kastner: On the Limits of Leakage Power Reduction in Caches. HPCA 2005: 154-165 | |
| 30 | Wenrui Gong, Gang Wang, Ryan Kastner: Storage assignment during high-level synthesis for configurable architectures. ICCAD 2005: 3-6 | |
| 29 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Energy Efficient Hardware Synthesis of Polynomial Expressions. VLSI Design 2005: 653-658 | |
| 28 | Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: A scheduling algorithm for optimization and early planning in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 10(1): 33-57 (2005) | |
| 27 | Yan Meng, Wenrui Gong, Ryan Kastner, Timothy Sherwood: Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator. J. Low Power Electronics 1(3): 238-248 (2005) | |
| 26 | Yan Meng, Timothy Sherwood, Ryan Kastner: Exploring the limits of leakage power reduction in caches. TACO 2(3): 221-246 (2005) | |
| 2004 | ||
| 25 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis. ASAP 2004: 202-212 | |
| 24 | Wenrui Gong, Gang Wang, Ryan Kastner: A High Performance Application Representation for Reconfigurable Systems. ERSA 2004: 218-224 | |
| 23 | Anup Hosangadi, Farzan Fallah, Ryan Kastner: Factoring and eliminating common subexpressions in polynomial expressions. ICCAD 2004: 169-174 | |
| 22 | Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh: Timing driven gate duplication. IEEE Trans. VLSI Syst. 12(1): 42-51 (2004) | |
| 2003 | ||
| 21 | Adam Kaplan, Philip Brisk, Ryan Kastner: Data communication estimation and reduction for reconfigurable systems. DAC 2003: 616-621 | |
| 20 | Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh: Congestion reduction during placement with provably good approximation bound. ACM Trans. Design Autom. Electr. Syst. 8(3): 316-333 (2003) | |
| 19 | Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: Creating and exploiting flexibility in rectilinear Steiner trees. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 605-615 (2003) | |
| 2002 | ||
| 18 | Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh: Instruction generation and regularity extraction for reconfigurable processors. CASES 2002: 262-269 | |
| 17 | Ryan Kastner, Christina Hsieh, Miodrag Potkonjak, Majid Sarrafzadeh: On the Sensitivity of Incremental Algorithms for Combinatorial Auctions. WECWIS 2002: 81-88 | |
| 16 | Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh: Instruction generation for hybrid reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. 7(4): 605-627 (2002) | |
| 15 | Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh: Congestion estimation during top-down placement. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 72-80 (2002) | |
| 14 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Pattern routing: use and theory for increasing predictability andavoiding coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 777-790 (2002) | |
| 2001 | ||
| 13 | Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: Creating and Exploiting Flexibility in Steiner Trees. DAC 2001: 195-198 | |
| 12 | Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Instruction Generation for Hybrid Reconfigurable Systems. ICCAD 2001: 127- | |
| 11 | Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh: A Super-Scheduler for Embedded Reconfigurable Systems. ICCAD 2001: 391- | |
| 10 | Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh: Congestion Reduction During Placement Based on Integer Programming. ICCAD 2001: 573-576 | |
| 9 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: An exact algorithm for coupling-free routing. ISPD 2001: 10-15 | |
| 8 | Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh: Congestion estimation during top-down placement. ISPD 2001: 164-169 | |
| 7 | Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava: Design and analysis of physical design algorithms. ISPD 2001: 82-89 | |
| 6 | Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh: On the complexity of gate duplication. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1170-1176 (2001) | |
| 2000 | ||
| 5 | Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh: A C to Hardware/Software Compiler. FCCM 2000: 331-332 | |
| 4 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh: Predictable Routing. ICCAD 2000: 110-113 | |
| 3 | Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh: Timing Driven Gate Duplication: Complexity Issues and Algorithms. ICCAD 2000: 447-450 | |
| 2 | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: Fast Template Placement for Reconfigurable Computing Systems. IEEE Design & Test of Computers 17(1): 68-83 (2000) | |
| 1999 | ||
| 1 | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping 1999: 38- | |