 | 2009 |
|---|
| 3 |       | Yoshiki Saito,
Toru Sano,
Masaru Kato,
Vasutan Tunbunheng,
Yoshihiro Yasuda,
Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
ERSA 2009: 283-286 |
| 2008 |
|---|
| 2 | | Masaru Kato,
Yohei Hasegawa,
Hideharu Amano:
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.
ERSA 2008: 215-221 |
| 1 |  | Toru Sano,
Masaru Kato,
Satoshi Tsutsumi,
Yohei Hasegawa,
Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
FPL 2008: 215-220 |
