Kentaroh Katoh

	2009
5		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Transactions 92-D(2): 336-341 (2009)
4		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Transactions 92-D(3): 433-442 (2009)
	2007
3		Abderrahim Doumar, Kentaroh Katoh, Hideo Ito: Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40
	2006
2		Kentaroh Katoh, Hideo Ito: Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. European Test Symposium 2006: 69-74
	2005
1		Kentaroh Katoh, Abderrahim Doumar, Hideo Ito: Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204

Coauthor Index

1	Abderrahim Doumar	[1] [3]
2	Hideo Ito	[1] [2] [3] [4] [5]
3	Kazuteru Namba	[4] [5]