| 2009 | ||
|---|---|---|
| 19 | Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller: CTL and Its Usage in the EDA Industry. IEEE Design & Test of Computers 26(1): 36-43 (2009) | |
| 2005 | ||
| 18 | Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161 | |
| 17 | Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman: Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470 | |
| 2004 | ||
| 16 | Vivek Chickermane, Brian Foutz, Brion L. Keller: Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC 2004: 452-461 | |
| 15 | Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane: An Economic Analysis and ROI Model for Nanometer Test. ITC 2004: 518-524 | |
| 2002 | ||
| 14 | Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera: Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Design & Test of Computers 19(5): 65-72 (2002) | |
| 2001 | ||
| 13 | Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater: A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium 2001: 325- | |
| 12 | Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller: High Performance Parallel Fault Simulation. ICCD 2001: 308-313 | |
| 11 | Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay: CTL the language for describing core-based test. ITC 2001: 131-139 | |
| 10 | Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko: OPMISR: the foundation for compressed ATPG vectors. ITC 2001: 748-757 | |
| 2000 | ||
| 9 | Paul Chang, Brion L. Keller, Sarala Paliwal: Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Asian Test Symposium 2000: 374-379 | |
| 8 | Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton: Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC 2000: 530-537 | |
| 1999 | ||
| 7 | Paul Chang, Brion L. Keller, Sarala Paliwal: Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ICCD 1999: 175- | |
| 6 | Brion L. Keller: Using STIL to describe embedded core test requirements. ITC 1999: 1150 | |
| 1998 | ||
| 5 | Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs: ATPG in practical and non-traditional applications. ITC 1998: 632-640 | |
| 1996 | ||
| 4 | Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr: Test methodologies and design automation for IBM ASICs. IBM Journal of Research and Development 40(4): 461-474 (1996) | |
| 1992 | ||
| 3 | Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams: Delay Test: The Next Frontier for LSSD Test Systems. ITC 1992: 578-587 | |
| 1991 | ||
| 2 | Brion L. Keller, David A. Haynes: Design Automation of Test for the EX/9000TM Series Processors. ICCD 1991: 550-553 | |
| 1 | Brion L. Keller, David P. Carlson, William Maloney: The Compiled Logic Simulator. IEEE Design & Test of Computers 8(1): 21-34 (1991) | |