 | 2009 |
| 25 |  | Andrew A. Kennings,
Kristofer Vorwerk,
Arun Kundu,
Val Pevzner,
Andy Fox:
FPGA technology mapping with encoded libraries andstaged priority cuts.
FPGA 2009: 143-150 |
| 24 |  | Val Pevzner,
Andrew A. Kennings,
Andy Fox:
Physical optimization for FPGAs using post-placement topology rewriting.
ISPD 2009: 91-98 |
| 23 |  | Kristofer Vorwerk,
Andrew A. Kennings,
Jonathan W. Greene:
Improving Simulated Annealing-Based FPGA Placement With Directed Moves.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 179-192 (2009) |
| 2008 |
| 22 |  | Ion I. Mandoiu,
Andrew A. Kennings:
The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings
ACM 2008 |
| 21 |  | Kristofer Vorwerk,
Madhu Raman,
Julien Dunoyer,
Yaun-chung Hsu,
Arun Kundu,
Andrew A. Kennings:
A technique for minimizing power during FPGA placement.
FPL 2008: 233-238 |
| 20 |  | Andrew A. Kennings,
Igor L. Markov:
Circuit Placement.
Encyclopedia of Algorithms 2008 |
| 2007 |
| 19 |  | Andrew A. Kennings,
Ion I. Mandoiu:
The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings
ACM 2007 |
| 18 |  | Kristofer Vorwerk,
Andrew A. Kennings,
Doris T. Chen,
Laleh Behjat:
Floorplan repair using dynamic whitespace management.
ACM Great Lakes Symposium on VLSI 2007: 552-557 |
| 17 |  | Doris T. Chen,
Kristofer Vorwerk,
Andrew A. Kennings:
Improving Timing-Driven FPGA Packing With Physical Information.
FPL 2007: 117-123 |
| 16 |  | Kristofer Vorwerk,
Andrew A. Kennings,
Jonathan W. Greene,
Doris T. Chen:
Improving Annealing Via Directed Moves.
FPL 2007: 363-370 |
| 15 |  | Jianhua Li,
Laleh Behjat,
Andrew A. Kennings:
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 669-679 (2007) |
| 2006 |
| 14 |  | Andrew A. Kennings,
Kristofer Vorwerk:
Force-Directed Methods for Generic Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2076-2087 (2006) |
| 2005 |
| 13 |  | Austin Hung,
William D. Bishop,
Andrew A. Kennings:
Symmetric Multiprocessing on Programmable Chips Made Easy.
DATE 2005: 240-245 |
| 12 |  | Kristofer Vorwerk,
Andrew A. Kennings:
An Improved Multi-Level Framework for Force-Directed Placement.
DATE 2005: 902-907 |
| 11 |  | Kristofer Vorwerk,
Andrew A. Kennings:
Mixed-size placement via line search.
ICCAD 2005: 899-904 |
| 10 |  | Miguel F. Anjos,
Andrew A. Kennings,
Anthony Vannelli:
A semidefinite optimization approach for the single-row layout problem with unequal dimensions.
Discrete Optimization 2(2): 113-122 (2005) |
| 2004 |
| 9 |  | Austin Hung,
William D. Bishop,
Andrew A. Kennings:
Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips.
ERSA 2004: 312 |
| 8 |  | Kristofer Vorwerk,
Andrew A. Kennings,
Anthony Vannelli:
Engineering details of a stable force-directed placer.
ICCAD 2004: 573-580 |
| 7 |  | William N. N. Hung,
Xiaoyu Song,
El Mostapha Aboulhamid,
Andrew A. Kennings,
Alan J. Coppola:
Segmented channel routability via satisfiability.
ACM Trans. Design Autom. Electr. Syst. 9(4): 517-528 (2004) |
| 2003 |
| 6 |  | Xiaoyu Song,
William N. N. Hung,
Alan Mishchenko,
Malgorzata Chrzanowska-Jeske,
Andrew A. Kennings,
Alan J. Coppola:
Board-level multiterminal net assignment for the partial cross-bar architecture.
IEEE Trans. VLSI Syst. 11(3): 511-514 (2003) |
| 2002 |
| 5 |  | Xiaoyu Song,
William N. N. Hung,
Alan Mishchenko,
Malgorzata Chrzanowska-Jeske,
Alan J. Coppola,
Andrew A. Kennings:
Board-level multiterminal net assignment.
ACM Great Lakes Symposium on VLSI 2002: 130-135 |
| 4 |  | William N. N. Hung,
Xiaoyu Song,
Alan J. Coppola,
Andrew A. Kennings:
On segmented channel routability.
ISCAS (1) 2002: 169-172 |
| 2000 |
| 3 |  | Andrew A. Kennings,
Igor L. Markov:
Analytical minimization of half-perimeter wirelength.
ASP-DAC 2000: 179-184 |
| 1999 |
| 2 |  | Ross Baldick,
Andrew B. Kahng,
Andrew A. Kennings,
Igor L. Markov:
Function Smoothing with Applications to VLSI Layout.
ASP-DAC 1999: 225- |
| 1 |  | Andrew E. Caldwell,
Andrew B. Kahng,
Andrew A. Kennings,
Igor L. Markov:
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.
DAC 1999: 349-354 |