Ming-Dou Ker

	2009
48		Ming-Dou Ker, Yuan-Wen Hsiao: Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits. IEICE Transactions 92-C(3): 341-351 (2009)
	2008
47		Ming-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng: ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. ISCAS 2008: 1292-1295
46		Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao: 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. ISCAS 2008: 820-823
45		Jung-Sheng Chen, Ming-Dou Ker: Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process. IEICE Transactions 91-C(3): 378-384 (2008)
44		Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng: Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. IEICE Transactions 91-C(8): 1321-1330 (2008)
	2007
43		Ming-Dou Ker, Hung-Tai Liao: Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. ISCAS 2007: 1121-1124
42		Ming-Dou Ker, Wei-Jen Chang: Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. Microelectronics Reliability 47(1): 27-35 (2007)
	2006
41		Ming-Dou Ker, Chien-Hua Wu: Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. ISCAS 2006
40		Zi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker: Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application. ISCAS 2006
39		Bo-Shih Huang, Ming-Dou Ker: New matching methodology of low-noise amplifier with ESD protection. ISCAS 2006
38		Hsin-Chyh Hsu, Ming-Dou Ker: Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. ISQED 2006: 503-506
37		Tai-Xiang Lai, Ming-Dou Ker: Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. ISQED 2006: 597-602
36		Chih-Kang Deng, Ming-Dou Ker: ESD robustness of thin-film devices with different layout structures in LTPS technology. Microelectronics Reliability 46(12): 2067-2073 (2006)
35		Kun-Hsien Lin, Ming-Dou Ker: Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board. Microelectronics Reliability 46(2-4): 301-310 (2006)
34		Shih-Hung Chen, Ming-Dou Ker: Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. Microelectronics Reliability 46(7): 1042-1049 (2006)
	2005
33		Kun-Hsien Lin, Ming-Dou Ker: ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. ISCAS (2) 2005: 1182-1185
32		Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai: Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. ISCAS (2) 2005: 1859-1862
31		Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu: New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. ISCAS (4) 2005: 3861-3864
30		Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu: A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device. IEICE Transactions 88-C(11): 2150-2155 (2005)
29		Ming-Dou Ker, Kun-Hsien Lin, Che-Hao Chuang: MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process. IEICE Transactions 88-C(3): 429-436 (2005)
28		Shih-Hung Chen, Ming-Dou Ker: Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology. Microelectronics Reliability 45(9-11): 1311-1316 (2005)
	2004
27		Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai: A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes. ISCAS (1) 2004: 321-324
26		Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu: A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device. ISCAS (1) 2004: 41-44
25		Shih-Lun Chen, Ming-Dou Ker: A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals. ISCAS (2) 2004: 573-576
24		Che-Hao Chuang, Ming-Dou Ker: Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. ISCAS (2) 2004: 577-580
23		Ming-Dou Ker, Kun-Hsien Lin: ESD protection design for IC with power-down-mode operation. ISCAS (2) 2004: 717-720
22		Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo: Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. ISQED 2004: 433-438
21		Ming-Dou Ker, Wen-Yi Chen: Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. ISQED 2004: 445-450
20		Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker: Design optimization of ESD protection and latchup prevention for a serial I/O IC. Microelectronics Reliability 44(2): 213-221 (2004)
	2003
19		Ming-Dou Ker, Chien-Ming Lee: Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. ISCAS (1) 2003: 297-300
18		Ming-Dou Ker, Chia-Sheng Tsai: Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. ISCAS (5) 2003: 97-100
17		Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang: Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. ISQED 2003: 241-
16		Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng: Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. ISQED 2003: 363-368
15		I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker: Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. Microelectronics Reliability 43(8): 1295-1301 (2003)
14		Wen-Yu Lo, Ming-Dou Ker: Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. Microelectronics Reliability 43(9-11): 1583-1588 (2003)
	2002
13		Ming-Dou Ker, Kuo-Chun Hsu: On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. ISCAS (5) 2002: 529-532
12		Ming-Dou Ker, Che-Hao Chuang: ESD protection circuits with novel MOS-bounded diode structures. ISCAS (5) 2002: 533-536
11		Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang: Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. ISCAS (5) 2002: 537-540
10		Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo: ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. ISQED 2002: 331-336
9		Ming-Dou Ker, Chyh-Yih Chang: ESD protection design for CMOS RF integrated circuits using polysilicon diodes. Microelectronics Reliability 42(6): 863-872 (2002)
	2001
8		Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win: ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. ISCAS (4) 2001: 754-757
7		Ming-Dou Ker, Tung-Yang Chen: Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. ISCAS (4) 2001: 758-761
6		Tung-Yang Chen, Ming-Dou Ker: Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. ISQED 2001: 247-248
5		Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang: Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. ISQED 2001: 267-272
4		Ming-Dou Ker, Yu-Yu Sung: Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard. Microelectronics Reliability 41(3): 417-429 (2001)
	1999
3		Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen: ESD buses for whole-chip ESD protection. ISCAS (1) 1999: 545-548
	1996
2		Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang: Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. IEEE Trans. VLSI Syst. 4(3): 307-321 (1996)
	1995
1		Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu: Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. ISCAS 1995: 833-836

Coauthor Index

1	Chyh-Yih Chang	[9]
2	Hun-Hsien Chang	[1] [2] [3]
3	Wei-Jen Chang	[22] [42]
4	Chuan-Jane Chao	[15] [20]
5	Jung-Sheng Chen	[26] [30] [31] [45]
6	S.-S. Chen	[5]
7	Shih-Hung Chen	[28] [34]
8	Shih-Lun Chen	[25] [27] [32]
9	Tung-Yang Chen	[3] [5] [6] [7] [8]
10	Wei-Fang Chen	[20]
11	Wen-Yi Chen	[21]
12	Zi-Ping Chen	[40]
13	Tao Cheng	[1] [2]
14	Fu-Chien Chiu	[20]
15	Ching-Yun Chu	[26] [30] [31]
16	Song-Yu Chuan	[20]
17	Che-Hao Chuang	[12] [24] [29] [40]
18	Chien-Hui Chuang	[10]
19	Chih-Kang Deng	[36]
20	Yuan-Wen Hsiao	[48]
21	Hsin-Chyh Hsu	[16] [38]
22	Kuo-Chun Hsu	[10] [13]
23	Bo-Shih Huang	[39]
24	Chih-Yao Huang	[15] [20]
25	Hsin-Chin Jiang	[11] [17]
26	Tai-Xiang Lai	[37]
27	Chien-Ming Lee	[19]
28	Len-Yi Leu	[20]
29	Hung-Tai Liao	[43] [46]
30	Chun-Yu Lin	[44] [47]
31	I-Cheng Lin	[15] [20]
32	Kun-Hsien Lin	[23] [29] [33] [35]
33	Wen-Yu Lo	[5] [10] [14] [22]
34	Guo-Xuan Meng	[44] [47]
35	Jeng-Jie Peng	[11] [16] [17]
36	Yu-Yu Sung	[4]
37	Howard Tang	[5]
38	Chia-Sheng Tsai	[18] [27] [32]
39	Jeng-Chou Tseng	[20]
40	M.-C. Wang	[5]
41	Tzu-Ming Wang	[46]
42	Chung-Yu Win	[8]
43	Chien-Hua Wu	[41]
44	Chung-Yu Wu	[1] [2]
45	Tain-Shun Wu	[1]

Colors in the list of coauthors