Lounis Kessal Coauthor index DBLP Vis pubzone.org

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12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNarayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal: Neural network hardware architecture for pattern recognition in the HESS2 project. ESANN 2008: 343-348
2007
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSi Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti: Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017]. Image Vision Comput. 25(6): 1032 (2007)
2006
10no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny: Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC 2006: 98-104
2004
9no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNicolas Abel, Lounis Kessal, Didier Demigny: Design flexibility using fpga dynamical reconfiguration. ICIP 2004: 2821-2824
2003
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLounis Kessal, Nicolas Abel, Didier Demigny: Real-time image processing with dynamically reconfigurable architecture. Real-Time Imaging 9(5): 297-313 (2003)
2001
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLP. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, M. Karabernou: Two ASIC for Low and Middle Levels of Real Time Image Processing. VLSI-SOC 2001: 3-14
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDidier Demigny, Lounis Kessal, J. Pons: Fast Recursive Implementation of the Gaussian Filter. VLSI-SOC 2001: 39-49
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, M. Karabernou: Reconfigurable Architecture Using High Speed FPGA. VLSI-SOC 2001: 75-86
2000
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDidier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani: How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? CAMP 2000: 240-
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLounis Kessal, Didier Demigny, N. Boudouani, R. Bourgiba: Reconfigurable Hardware for Real Time Image Processing. ICIP 2000
1997
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLF. G. Lorca, Lounis Kessal, Didier Demigny: Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. ICIP (2) 1997: 406-409
1995
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDidier Demigny, F. G. Lorca, Lounis Kessal: Evaluation of edge detectors performances with a discrete expression of Canny's criteria. ICIP 1995: 2169-2172

Coauthor Index

1Nicolas Abel [8] [9] [10]
2N. Boudouani [3] [4] [5]
3R. Bourgiba [3]
4R. Bourguiba [4] [5]
5Didier Demigny [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
6M. Karabernou [5] [7]
7Si Mahmoud Karabernou [11]
8Sonia Khatchadourian [12]
9P. Lamaty [7]
10F. G. Lorca [1] [2]
11B. Mazar [7]
12Sébastien Pillement [10]
13J. Pons [6]
14Jean-Christophe Prévotet [12]
15Narayanan Ramanan [12]
16Fayçal Terranti [11]

Colors in the list of coauthors

Copyright © Mon Nov 30 15:58:31 2009 by Michael Ley (ley@uni-trier.de)