Sunil P. Khatri

	2009
82		Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri: Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362
81		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
80		Kanupriya Gulati, Sunil P. Khatri: Accelerating statistical static timing analysis using graphics processing units. ASP-DAC 2009: 260-265
79		Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry: Fast circuit simulation on graphics processing units. ASP-DAC 2009: 403-408
78		Rajesh Garg, Sunil P. Khatri: Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC 2009: 461-467
77		Kanupriya Gulati, Sunil P. Khatri, Peng Li: Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287
76		Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya: Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672
75		Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
74		Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
	2008
73		Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri: A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122
72		Kanupriya Gulati, Sunil P. Khatri: Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150
71		Suganth Paul, Rajesh Garg, Sunil P. Khatri: Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218
70		Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320
69		Kanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827
68		Rajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923
67		Chunjie Duan, Chengyu Zhu, Sunil P. Khatri: Forbidden transition free crosstalk avoidance CODEC design. DAC 2008: 986-991
66		Charu Nagpal, Rajesh Garg, Sunil P. Khatri: A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359
65		Chunjie Duan, Sunil P. Khatri: Energy Efficient and High Speed On-Chip Ternary Bus. DATE 2008: 515-518
64		Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri: A Single-supply True Voltage Level Shifter. DATE 2008: 979-984
63		Victor H. Cordero, Sunil P. Khatri: Clock Distribution Scheme using Coplanar Transmission Lines. DATE 2008: 985-990
62		Rajesh Garg, Sunil P. Khatri: A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20
61		Rajesh Garg, Peng Li, Sunil P. Khatri: Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791
60		Sabyasachi Das, Sunil P. Khatri: A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design 2008: 572-579
59		Sabyasachi Das, Sunil P. Khatri: A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. VLSI Design 2008: 635-640
58		Sabyasachi Das, Sunil P. Khatri: An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. VLSI Design 2008: 653-659
57		Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
56		Sabyasachi Das, Sunil P. Khatri: Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
55		Sabyasachi Das, Sunil P. Khatri: A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Trans. VLSI Syst. 16(3): 326-331 (2008)
54		A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: Dynamically De-Skewable Clock Distribution Methodology. IEEE Trans. VLSI Syst. 16(9): 1220-1229 (2008)
53		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008)
	2007
52		Nikhil Jayakumar, Sunil P. Khatri: An algorithm to minimize leakage through simultaneous input vector control and circuit modification. DATE 2007: 618-623
51		Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279
50		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790
49		Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri: A methodology for interconnect dimension determination. ISPD 2007: 189-195
48		Nikhil Jayakumar, Sunil P. Khatri: A Predictably Low-Leakage ASIC Design Style. IEEE Trans. VLSI Syst. 15(3): 276-285 (2007)
47		Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri: High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. VLSI Signal Processing 49(1): 185-206 (2007)
	2006
46		Bo Shen, Sunil P. Khatri, Takis Zourntos: Implementation of MOSFET based capacitors for digital applications. ACM Great Lakes Symposium on VLSI 2006: 180-186
45		Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
44		Scott J. Campbell, Sunil P. Khatri: Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI 2006: 308-311
43		Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri: Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855
42		Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424
41		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
40		Brock J. LaMeres, Sunil P. Khatri: Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. DATE 2006: 522-527
39		Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson: Network coding for routability improvement in VLSI. ICCAD 2006: 820-823
38		Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi: An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006
37		Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri: CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006
36		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri: On the Improvement of Statistical Static Timing Analysis. ICCD 2006
35		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006
34		Chunjie Duan, Sunil P. Khatri: Computing during supply voltage switching in DVS enabled real-time processors. ISCAS 2006
33		Kanupriya Gulati, M. Lovell, Sunil P. Khatri: Efficient don't care computation for hierarchical designs. ISCAS 2006
32		Rajesh Garg, Sunil P. Khatri: Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006
31		Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri: Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006
	2005
30		Van R. Culver, Sunil P. Khatri: A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. ASP-DAC 2005: 842-845
29		Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri: A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. DAC 2005: 43-46
28		Nikhil Jayakumar, Sunil P. Khatri: A variation tolerant subthreshold design approach. DAC 2005: 716-719
27		Brock J. LaMeres, Sunil P. Khatri: Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. DATE 2005: 1318-1323
26		Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
25		Nikhil Jayakumar, Sunil P. Khatri: Minimum Energy Near-threshold Network of PLA based Design. ICCD 2005: 399-404
24		Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra: X-Routing using Two Manhattan Route Instances. ICCD 2005: 45-52
23		Brock J. LaMeres, Sunil P. Khatri: Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. ICCD 2005: 683-688
22		Brock J. LaMeres, Sunil P. Khatri: Performance model for inter-chip communication considering inductive cross-talk and cost. ISCAS (4) 2005: 4130-4133
21		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114
20		Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri: Non-Manhattan Routing Using a Manhattan Router. VLSI Design 2005: 445-450
	2004
19		Nikhil Saluja, Sunil P. Khatri: A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC 2004: 422-427
18		Chunjie Duan, Sunil P. Khatri: Exploiting Crosstalk to Speed up On-Chip Buse. DATE 2004: 778-783
17		Nikhil Jayakumar, Sunil P. Khatri: A metal and via maskset programmable VLSI design methodology using PLAs. ICCAD 2004: 590-594
16		A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri: A novel clock distribution and dynamic de-skewing methodology. ICCAD 2004: 626-631
15		Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1020-1030 (2004)
	2003
14		Nikhil Jayakumar, Sunil P. Khatri: An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ISLPED 2003: 128-133
	2002
13		Sabyasachi Das, Sunil P. Khatri: An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 93-101 (2002)
	2001
12		Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli: Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD 2001: 224-231
11		Sabyasachi Das, Sunil P. Khatri: A regularity-driven fast gridless detailed router for high frequency datapath designs. ISPD 2001: 130-135
	2000
10		Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418
9		Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
	1999
8		Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496
7		Robert K. Brayton, Sunil P. Khatri: Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105
6		Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211
	1996
5		Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432
4		Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456
3		Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256
2		Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434
1		Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253

Coauthor Index

1	Seraj Ahmad	[24]
2	Charles J. Alpert	[26]
3	Adnan Aziz	[3] [5]
4	Vijay Balasubramanian	[24]
5	Kalyana C. Bollapalli	[81]
6	Robert K. Brayton	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [15]
7	Scott J. Campbell	[44]
8	Mosong Cheng	[70]
9	Szu-Tsung Cheng	[3] [5]
10	Gwan S. Choi (Gwan Choi)	[41] [75]
11	Jeff L. Cobb	[49] [82]
12	C. Coelho	[2]
13	Victor H. Cordero	[63]
14	John F. Croix	[79]
15	Van R. Culver	[30]
16	Sabyasachi Das	[11] [13] [55] [56] [58] [59] [60]
17	Rajballav Dash	[75]
18	Sandeep Dhar	[29]
19	Chunjie Duan	[18] [31] [34] [65] [67]
20	Stephen A. Edwards	[3] [5]
21	Masahiro Fujita	[1] [2]
22	Bruce Gamache	[42]
23	Rajesh Garg	[32] [36] [37] [41] [42] [45] [49] [61] [62] [64] [66] [68] [70] [71] [73] [75] [76] [78] [81]
24	Eugene Goldberg (Evguenii I. Goldberg)	[51]
25	Salman Gopalani	[70]
26	Wilsin Gosti	[12]
27	Kanupriya Gulati	[21] [31] [33] [35] [38] [39] [43] [45] [50] [51] [53] [57] [69] [72] [74] [77] [79] [80] [81] [82]
28	Anshul Gupta	[45]
29	Gary D. Hachtel	[3] [5]
30	Jiang Hu	[26]
31	Edward Hursey	[20] [24]
32	Jawahar Jain	[1] [2]
33	Abhijit Jas	[74]
34	Nikhil Jayakumar	[14] [16] [17] [20] [21] [24] [25] [26] [28] [29] [35] [36] [39] [41] [42] [45] [47] [48] [50] [52] [53] [54]
35	A. Kapoor	[16] [54]
36	Sriram C. Krishnan	[4]
37	Yuji Kukimoto	[3] [5]
38	Brock J. LaMeres	[22] [23] [27] [40] [43]
39	Stefan Laendner	[47]
40	Peng Li	[26] [61] [77]
41	M. Lovell	[33]
42	Dumezie Maduike	[37]
43	Rabi N. Mahapatra	[24]
44	Gagandeep Mallarapu	[64]
45	Patrick McGuinness	[26]
46	Kenneth L. McMillan	[4]
47	Amit Mehrotra	[8]
48	Eric Menendez	[37]
49	Olgica Milenkovic	[47]
50	Vijay Nagarajan	[47]
51	Charu Nagpal	[66] [68]
52	Amit Narayan	[1] [2] [4]
53	Ralph H. J. M. Otten	[8]
54	Abelardo Pardo	[3] [5]
55	Srinivas Patil	[74]
56	Suganth Paul	[71] [74] [76]
57	Shaz Qadeer	[3] [5]
58	Anand Rajaram	[26]
59	Rajeev K. Ranjan	[3] [5]
60	Nikhil Saluja	[19] [57]
61	Mario Sanchez	[45]
62	Alberto L. Sangiovanni-Vincentelli	[1] [2] [3] [4] [5] [6] [8] [9] [10] [12] [15]
63	Shaker Sarwary	[3] [5]
64	Rahm Shastry	[79]
65	Bo Shen	[46]
66	Weiping Shi	[38]
67	Thomas R. Shiple	[3] [5]
68	Subarnarekha Sinha	[9] [15]
69	Fabio Somenzi	[3] [5]
70	Alexander Sprintson	[39]
71	Gitanjali Swamy	[3] [5]
72	Sheila Vaidya	[76]
73	Ganesh Venkataraman	[26]
74	Arunprasad Venkatraman	[73]
75	Tiziano Villa	[3] [5]
76	Mandar Waghmode	[38]
77	D. M. H. Walker (Duncan M. Hank Walker)	[53]
78	Chengyu Zhu	[67]
79	Takis Zourntos	[46]

Colors in the list of coauthors