Chris H. Kim Coauthor index DBLP Vis pubzone.org

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DBLP keys2009
36Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289
35Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKi Chul Chun, Pulkit Jain, Chris H. Kim: A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED 2009: 119-120
2008
34Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim: Circuit techniques for ultra-low power subthreshold SRAMs. ISCAS 2008: 2574-2577
33Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim: Enhancing beneficial jitter using phase-shifted clock distribution. ISLPED 2008: 21-26
32Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim: A multi-story power delivery technique for 3D integrated circuits. ISLPED 2008: 57-62
31Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim: Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. VLSI Syst. 16(2): 206-209 (2008)
30Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. VLSI Syst. 16(3): 249-262 (2008)
29Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJonggab Kil, Jie Gu, Chris H. Kim: A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. IEEE Trans. VLSI Syst. 16(4): 456-465 (2008)
28Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. VLSI Syst. 16(5): 598-602 (2008)
2007
27Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274
26Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375
25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJie Gu, Sachin S. Sapatnekar, Chris H. Kim: Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92
24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJohn Keane, Tae-Hyoung Kim, Chris H. Kim: An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ISLPED 2007: 189-194
23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJie Gu, Hanyong Eom, Chris H. Kim: Sleep transistor sizing and control for resonant supply noise damping. ISLPED 2007: 80-85
22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513
21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas: Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim: Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. IEEE Trans. VLSI Syst. 15(7): 821-829 (2007)
2006
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: An analytical model for negative bias temperature instability. ICCAD 2006: 493-496
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim: Utilizing reverse short channel effect for optimal subthreshold circuit design. ISLPED 2006: 127-130
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJie Gu, John Keane, Chris H. Kim: Modeling and analysis of leakage induced damping effect in low voltage LSIs. ISLPED 2006: 382-387
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJonggab Kil, Jie Gu, Chris H. Kim: A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. ISLPED 2006: 67-72
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAmit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006)
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 646-649 (2006)
2005
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJie Gu, Chris H. Kim: Multi-story power delivery for supply noise reduction and low voltage operation. ISLPED 2005: 192-197
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKee-Jong Kim, Chris H. Kim, Kaushik Roy: TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
2004
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAmit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHari Ananthan, Chris H. Kim, Kaushik Roy: Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13
2003
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSaibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003)
2002
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Kaushik Roy: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChris H. Kim, Kaushik Roy: Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254

Coauthor Index

1Amit Agarwal [3] [6] [12]
2Hari Ananthan [5]
3Shekhar Y. Borkar (Shekhar Borkar) [10] [11]
4Paulo F. Butzen [21] [22] [27]
5R. T. Cakici [3]
6Ki Chul Chun [35]
7Hanyong Eom [16] [18] [20] [23] [28]
8Jie Gu [9] [14] [15] [23] [25] [29] [31] [33]
9Steven Hsu [10] [11]
10Pulkit Jain [32] [33] [35]
11Dong Jiao [33]
12John Keane [15] [16] [18] [20] [24] [28] [31] [32] [34]
13Jonggab Kil [14] [29]
14Jae-Joon Kim [4] [7]
15Kee-Jong Kim [8]
16Tae-Hyoung Kim [16] [18] [20] [24] [28] [32] [34]
17Ram Krishnamurthy [10] [11]
18Sanjay V. Kumar [13] [17] [19] [26] [30] [36]
19Jason Liu [34]
20Saibal Mukhopadhyay [3] [4] [6] [7] [12]
21Cassondra Neau [3]
22Arijit Raychowdhury [12]
23André Inácio Reis [21] [22] [27]
24Renato P. Ribas [21] [22] [27]
25Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12]
26Sachin S. Sapatnekar [13] [17] [18] [19] [25] [26] [28] [30] [31] [36]

Colors in the list of coauthors

Copyright © Fri Nov 27 15:43:12 2009 by Michael Ley (ley@uni-trier.de)