 | 2009 |
|---|
| 88 |       | HaNeul Chon,
Taewhan Kim:
Timing variation-aware task scheduling and binding for MPSoC.
ASP-DAC 2009: 137-142 |
| 87 | | Hochang Jang,
Taewhan Kim:
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
DAC 2009: 794-799 |
| 86 | | ByungHyun Lee,
Ki-Seok Chung,
Bontae Koo,
Nak-Woong Eum,
Taewhan Kim:
Thermal sensor allocation and placement for reconfigurable systems.
ACM Trans. Design Autom. Electr. Syst. 14(4): (2009) |
| 85 | | Pilok Lim,
Ki-Seok Chung,
Taewhan Kim:
Thermal-Aware High-Level Synthesis Based on Network Flow Method.
Journal of Circuits, Systems, and Computers 18(5): 965-984 (2009) |
| 2008 |
|---|
| 84 | | ByungHyun Lee,
Taewhan Kim:
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension.
ASP-DAC 2008: 703-707 |
| 83 | | Yongho Lee,
Deog-Kyoon Jeong,
Taewhan Kim:
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
ICCAD 2008: 169-172 |
| 82 | | Yesin Ryu,
Taewhan Kim:
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.
ICCAD 2008: 416-419 |
| 81 | | Eunjoo Choi,
Changsik Shin,
Taewhan Kim,
Youngsoo Shin:
Power-gating-aware high-level synthesis.
ISLPED 2008: 39-44 |
| 80 | | Soonhoi Ha,
Kiyoung Choi,
Taewhan Kim,
Krisztián Flautner,
Sang Lyul Min,
Wang Yi:
Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 79 | | Benjamin Carrión Schäfer,
Taewhan Kim:
Hotspots Elimination and Temperature Flattening in VLSI Circuits.
IEEE Trans. VLSI Syst. 16(11): 1475-1487 (2008) |
| 2007 |
|---|
| 78 |  | Taewhan Kim,
Pascal Sainrat,
Steven S. Lumetta,
Nacho Navarro:
Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007
ACM 2007 |
| 77 | | Kyoung-Hwan Lim,
YongHwan Kim,
Taewhan Kim:
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.
DAC 2007: 765-770 |
| 76 | | Jongyoon Jung,
Taewhan Kim:
Timing variation-aware high-level synthesis.
ICCAD 2007: 424-428 |
| 75 | | Zhenmin Li,
Taewhan Kim:
Address Code Optimization Exploiting Code Scheduling in DSP Applications.
ISCAS 2007: 1573-1576 |
| 74 | | Benjamin Carrión Schäfer,
Yongho Lee,
Taewhan Kim:
Temperature-Aware Compilation for VLIWProcessors.
RTCSA 2007: 426-431 |
| 73 | | Taewhan Kim,
Jungeun Kim:
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 142-151 (2007) |
| 72 | | Yongseok Choi,
Naehyuck Chang,
Taewhan Kim:
DC-DC Converter-Aware Power Management for Low-Power Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1367-1381 (2007) |
| 2006 |
|---|
| 71 | | Seongsoo Hong,
Wayne Wolf,
Krisztián Flautner,
Taewhan Kim:
Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006
ACM 2006 |
| 70 | | Young-Jun Kim,
Taewhan Kim:
HW/SW partitioning techniques for multi-mode multi-task embedded applications.
ACM Great Lakes Symposium on VLSI 2006: 25-30 |
| 69 | | Pilok Lim,
Taewhan Kim:
Thermal-aware high-level synthesis based on network flow method.
CODES+ISSS 2006: 124-129 |
| 68 | | Junhyung Um,
Woo-Cheol Kwon,
Sungpack Hong,
Young-Taek Kim,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo,
Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design.
DATE 2006: 560-564 |
| 67 | | Taewhan Kim:
Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling.
RTCSA 2006: 199-206 |
| 66 | | Jaewon Seo,
Taewhan Kim,
Joonwon Lee:
Optimal intratask dynamic voltage-scaling technique and its practical extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 47-57 (2006) |
| 65 | | Yoonseo Choi,
Taewhan Kim:
Memory Access Driven Storage Assignment for Variables in Embedded System Design.
Journal of Circuits, Systems, and Computers 15(2): 145-168 (2006) |
| 64 | | Junhyung Um,
Taewhan Kim:
Resource Sharing Combined with Layout Effects in High-Level Synthesis.
VLSI Signal Processing 44(3): 231-243 (2006) |
| 63 | | Young-Jun Kim,
Taewhan Kim:
A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications.
VLSI Signal Processing 44(3): 269-283 (2006) |
| 2005 |
|---|
| 62 | | Jungeun Kim,
Taewhan Kim:
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.
DAC 2005: 105-110 |
| 61 | | Yongseok Choi,
Naehyuck Chang,
Taewhan Kim:
DC-DC converter-aware power management for battery-operated embedded systems.
DAC 2005: 895-900 |
| 60 | | Jaewon Seo,
Taewhan Kim,
Nikil D. Dutt:
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
ICCAD 2005: 450-455 |
| 59 | | Woo-Cheol Kwon,
Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors.
ACM Trans. Embedded Comput. Syst. 4(1): 211-230 (2005) |
| 58 | | Yoonseo Choi,
Taewhan Kim,
Hwansoo Han:
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 278-287 (2005) |
| 2004 |
|---|
| 57 | | Keoncheol Shin,
Taewhan Kim:
Leakage power minimization for the synthesis of parallel multiplier circuits.
ACM Great Lakes Symposium on VLSI 2004: 166-169 |
| 56 | | Keoncheol Shin,
Taewhan Kim:
An integrated approach to timing-driven synthesis and placement of arithmetic circuits.
ASP-DAC 2004: 155-158 |
| 55 | | Yoonseo Choi,
Taewhan Kim:
Memory access driven storage assignment for variables in embedded system design.
ASP-DAC 2004: 478-481 |
| 54 | | Meeyoung Cha,
Chun-Gi Lyuh,
Taewhan Kim:
Resource-constrained low-power bus encoding with crosstalk delay elimination.
ASP-DAC 2004: 834-837 |
| 53 | | Chun-Gi Lyuh,
Taewhan Kim:
Memory access scheduling and binding considering energy minimization in multi-bank memory systems.
DAC 2004: 81-86 |
| 52 | | Jaewon Seo,
Taewhan Kim,
Ki-Seok Chung:
Profile-based optimal intra-task voltage scheduling for hard real-time applications.
DAC 2004: 87-92 |
| 51 | | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
IEEE Trans. Computers 53(7): 829-842 (2004) |
| 50 | | Keoncheol Shin,
Taewhan Kim:
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.
IEEE Trans. VLSI Syst. 12(7): 766-775 (2004) |
| 49 | | Chun-Gi Lyuh,
Taewhan Kim,
Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis [IC layout].
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 157-164 (2004) |
| 2003 |
|---|
| 48 | | Woo-Cheol Kwon,
Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors.
DAC 2003: 125-130 |
| 47 | | Yoonseo Choi,
Taewhan Kim:
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
DAC 2003: 881-886 |
| 46 | | Junhyung Um,
Taewhan Kim:
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.
ICCAD 2003: 197-200 |
| 45 | | Ki-Wook Kim,
Seong-Ook Jung,
Taewhan Kim,
Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) |
| 44 | | Chun-Gi Lyuh,
Taewhan Kim:
High-level synthesis for low power based on network flow method.
IEEE Trans. VLSI Syst. 11(3): 364-375 (2003) |
| 43 | | Ki-Wook Kim,
Seong-Ook Jung,
Taewhan Kim,
Prashant Saxena,
C. L. Liu,
S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. VLSI Syst. 11(5): 879-887 (2003) |
| 42 | | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. VLSI Syst. 11(5): 928-938 (2003) |
| 41 | | Junhyung Um,
Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1487-1503 (2003) |
| 40 | | Yoonseo Choi,
Taewhan Kim:
Address assignment in DSP code generation - an integrated approach.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 976-984 (2003) |
| 39 | | Sungpack Hong,
Taewhan Kim:
Bus Optimization for Low Power in High-Level Synthesis.
Journal of Circuits, Systems, and Computers 12(1): 1-18 (2003) |
| 2002 |
|---|
| 38 | | Junhyung Um,
Taewhan Kim:
Layout-aware synthesis of arithmetic circuits.
DAC 2002: 207-212 |
| 37 | | Yoonseo Choi,
Taewhan Kim:
Address assignment combined with scheduling in DSP code generation.
DAC 2002: 225-230 |
| 36 | | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis.
DAC 2002: 608-611 |
| 35 | | Chun-Gi Lyuh,
Taewhan Kim,
Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis for low power.
ICCAD 2002: 609-613 |
| 34 | | Junhyung Um,
Jae-hoon Kim,
Taewhan Kim:
Layout-driven resource sharing in high-level synthesis.
ICCAD 2002: 614-618 |
| 33 | | Yoonseo Choi,
Taewhan Kim:
An efficient low-power binding algorithm in high-level synthesis.
ISCAS (4) 2002: 321-324 |
| 32 | | Jaewon Seo,
Taewhan Kim:
Memory exploration utilizing scheduling effects in high-level synthesis.
ISCAS (4) 2002: 73-76 |
| 31 | | Unni Narayanan,
Ki-Seok Chung,
Taewhan Kim:
Enhanced bus invert encodings for low-power.
ISCAS (5) 2002: 25-28 |
| 30 | | Yoonseo Choi,
Taewhan Kim:
Address code optimization using code scheduling for digital signal processors.
ISCAS (5) 2002: 481-484 |
| 29 | | Ki-Wook Kim,
Taewhan Kim,
TingTing Hwang,
Sung-Mo Kang,
C. L. Liu:
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) |
| 28 | | Ki-Wook Kim,
Taewhan Kim,
C. L. Liu,
Sung-Mo Kang:
Domino logic synthesis based on implication graph.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002) |
| 27 | | Ki-Seok Chung,
Taewhan Kim,
C. L. Liu:
A Complete Model for Glitch Analysis in Logic Circuits.
Journal of Circuits, Systems, and Computers 11(2): 137-154 (2002) |
| 26 | | Yoonseo Choi,
Taewhan Kim:
Binding Algorithm for Power Optimization Based on Network Flow Method.
Journal of Circuits, Systems, and Computers 11(3): 259-272 (2002) |
| 25 | | Ki-Seok Chung,
Rajesh K. Gupta,
Taewhan Kim,
C. L. Liu:
Synthesis and Optimization of Combinational Interface Circuits.
VLSI Signal Processing 31(3): 243-261 (2002) |
| 2001 |
|---|
| 24 | | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
An accurate evaluation of routing density for symmetrical FPGAs.
ACM Great Lakes Symposium on VLSI 2001: 51-55 |
| 23 | | Youngtae Kim,
Taewhan Kim:
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.
ASP-DAC 2001: 622-628 |
| 22 | | Taewhan Kim,
Ki-Seok Chung,
Chien-Liang Liu:
A Static Estimation Technique of Power Sensitivity in Logic Circuits.
DAC 2001: 215-219 |
| 21 | | Nak-Woong Eum,
Taewhan Kim,
Chong-Min Kyung:
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
ICCAD 2001: 137-143 |
| 20 | | Chun-Gi Lyuh,
Taewhan Kim,
Chien-Liang Liu:
An Integrated Data Path Optimization for Low Power Based on Network Flow Method.
ICCAD 2001: 553-559 |
| 19 | | Junhyung Um,
Taewhan Kim:
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.
IEEE Trans. Computers 50(3): 215-233 (2001) |
| 18 | | Ki-Seok Chung,
Taewhan Kim,
C. L. Liu:
G-vector: A New Model for Glitch Analysis in Logic Circuits.
VLSI Signal Processing 27(3): 235-251 (2001) |
| 2000 |
|---|
| 17 | | Ki-Seok Chung,
Taewhan Kim,
Chien-Liang Liu:
Behavioral-level partitioning for low power design in control-dominated application.
ACM Great Lakes Symposium on VLSI 2000: 156-161 |
| 16 | | Taewhan Kim,
Junhyung Um:
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).
ASP-DAC 2000: 313-316 |
| 15 | | Junhyung Um,
Taewhan Kim,
C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.
DAC 2000: 98-103 |
| 14 | | Sungpack Hong,
Taewhan Kim:
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method.
ICCAD 2000: 312-317 |
| 13 | | Gernot Koch,
Taewhan Kim,
Reiner Genevriere:
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis.
ICCAD 2000: 33-38 |
| 12 | | Taewhan Kim,
Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 615-624 (2000) |
| 11 | | Sungpack Hong,
Taewhan Kim,
Unni Narayanan,
Ki-Seok Chung:
Decomposition of Bus-Invert Coding for Low-Power I/O.
Journal of Circuits, Systems, and Computers 10(1-2): 101-112 (2000) |
| 10 | | Youngtae Kim,
Taewhan Kim:
An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.
Journal of Circuits, Systems, and Computers 10(5-6): 279-292 (2000) |
| 1999 |
|---|
| 9 | | Junhyung Um,
Taewhan Kim,
C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization.
ICCAD 1999: 410-413 |
| 1998 |
|---|
| 8 | | Taewhan Kim,
William Jao,
Steven W. K. Tjiang:
Arithmetic Optimization Using Carry-Save-Adders.
DAC 1998: 433-438 |
| 7 | | Taewhan Kim,
William Jao,
Steven W. K. Tjiang:
Circuit optimization using carry-save-adder cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 974-984 (1998) |
| 6 | | Chaeryung Park,
Taewhan Kim,
C. L. Liu:
Register Allocation - A Hierarchical Reduction Approach.
VLSI Signal Processing 19(3): 269-285 (1998) |
| 1996 |
|---|
| 5 | | Taewhan Kim,
C. L. Liu:
An integrated algorithm for incremental data path synthesis.
VLSI Signal Processing 12(3): 265-285 (1996) |
| 1994 |
|---|
| 4 | | Taewhan Kim,
Ki-Seok Chung,
Chien-Liang Liu:
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.
EDAC-ETC-EUROASIC 1994: 586-590 |
| 3 | | Taewhan Kim,
Noritake Yonezawa,
Jane W.-S. Liu,
C. L. Liu:
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 425-438 (1994) |
| 1993 |
|---|
| 2 | | Taewhan Kim,
C. L. Liu:
Utilization of Multiport Memories in Data Path Synthesis.
DAC 1993: 298-302 |
| 1991 |
|---|
| 1 | | Taewhan Kim,
Jane W.-S. Liu,
C. L. Liu:
A Scheduling Algorithm for Conditional Resource Sharing.
ICCAD 1991: 84-87 |
