Shinji Kimura

	2009
27		Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi: An objective and subjective evaluation of an autostereoscopic 3d display. CHI Extended Abstracts 2009: 3577-3582
26		Chengjie Zang, Shinji Kimura: Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. IEICE Transactions 92-A(6): 1454-1463 (2009)
	2008
25		Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Synthesis of parallel prefix adders considering switching activities. ICCD 2008: 404-409
24		Yun Yang, Shinji Kimura: Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration. IEICE Transactions 91-A(12): 3431-3442 (2008)
23		Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura: Fine-Grained Power Gating Based on the Controlling Value of Logic Elements. IEICE Transactions 91-A(12): 3531-3538 (2008)
22		Chengjie Zang, Shigeki Imai, Steven Frank, Shinji Kimura: Issue Mechanism for Embedded Simultaneous Multithreading Processor. IEICE Transactions 91-A(4): 1092-1100 (2008)
21		Yun Yang, Shinji Kimura: The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array. IEICE Transactions 91-A(4): 1101-1111 (2008)
	2006
20		Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya: Transition-based coverage estimation for symbolic model checking. ASP-DAC 2006: 1-6
19		Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658
18		Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura: Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique. IEICE Transactions 89-A(12): 3427-3434 (2006)
17		Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya: Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification. IEICE Transactions 89-A(12): 3451-3457 (2006)
16		Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Transactions 89-A(4): 996-1004 (2006)
	2005
15		Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura: Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389
14		Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura: A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection. IPDPS 2005
13		Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya: Extended abstract: transition traversal coverage estimation for symbolic model checking. MEMOCODE 2005: 259-260
12		Shinji Kimura: Special Section on VLSI Design and CAD Algorithms. IEICE Transactions 88-A(12): 3273 (2005)
	2004
11		Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura: Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. ASP-DAC 2004: 80-85
10		Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437
	2002
9		Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara: Folding of logic functions and its application to look up table compaction. ICCAD 2002: 694-697
	2001
8		Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC 2001: 31-32
7		Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: Speech recognition chip for monosyllables. ASP-DAC 2001: 396-399
	2000
6		Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe: An application specific Java processor with reconfigurabilities. ASP-DAC 2000: 25-26
5		Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe: Multi-clock path analysis using propositional satisfiability. ASP-DAC 2000: 81-86
	1998
4		Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe: Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395
	1997
3		Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya: A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES 1997: 147-152
	1995
2		Shinji Kimura: Residue BDD and Its Application to the Verification of Arithmetic Circuits. DAC 1995: 542-545
	1992
1		Shinji Kimura, Shigemi Kashima, Hiromasa Haneda: Precise timing verification of logic circuits under combined delay model. ICCAD 1992: 526-529

Coauthor Index

1	Tatsumori Abematsu	[6]
2	Lei Chen	[23]
3	Nobuhiro Doi	[11] [18]
4	Steven Frank	[22]
5	Hiromasa Haneda	[1]
6	Tatsuo Hiramatsu	[14]
7	Makoto Hirao	[3]
8	Katsunori Hirase	[14]
9	Kazunari Horikawa	[13] [17] [20]
10	Tsutomu Horikoshi	[27]
11	Takashi Horiyama	[7] [8] [9] [11] [18] [23]
12	Shigeki Imai	[22]
13	Yasufumi Itou	[3]
14	Hirotsugu Kajihara	[9]
15	Shigemi Kashima	[1]
16	Hiroyuki Kida	[6]
17	Shinji Maruoka	[5] [7] [8]
18	Taeko Matsunaga	[25]
19	Yusuke Matsunaga	[25]
20	Akira Nagoya	[3]
21	Hiroshi Nakajima	[14]
22	Kazuhiro Nakamura	[4] [5] [7] [8]
23	Yuichi Nakamura (Yuhichi Nakamura)	[23]
24	Masaki Nakanishi	[9] [11] [18]
25	Tatsuo Ohtsuki	[10] [15] [16] [19]
26	Makoto Okada	[14]
27	Makoto Ozone	[14]
28	Youhua Shi	[10] [15] [16] [19]
29	Kazuyoshi Takagi	[4] [6]
30	Nozomu Togawa	[10] [15] [16] [19]
31	Masashi Tsuboi	[27]
32	Takehiko Tsuchiya	[13] [17] [20]
33	Katsumasa Watanabe	[3] [4] [5] [6] [7] [8]
34	Xingwen Xu	[13] [17] [20]
35	Masao Yanagisawa	[10] [15] [16] [19]
36	Yun Yang	[21] [24]
37	Mitsuteru Yukishita	[3]
38	Chengjie Zang	[22] [26]
39	Qiang Zhu	[7] [8]

Colors in the list of coauthors