Fuminori Kobayashi

	2008
24		Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe: MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA 2008: 222-228
	2007
23		Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi: 272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA 2007: 259-264
22		Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi: A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS 2007: 1-7
21		Minoru Watanabe, Fuminori Kobayashi: Holographic memory reconfigurable VLSI. ISCAS 2007: 401-404
	2006
20		Minoru Watanabe, Fuminori Kobayashi: A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC 2006: 268-273
19		Minoru Watanabe, Fuminori Kobayashi: A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC 2006: 108-109
18		Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi: Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA 2006: 198-206
17		Minoru Watanabe, Fuminori Kobayashi: Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA 2006: 237-238
16		Minoru Watanabe, Fuminori Kobayashi: Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA 2006: 239-240
15		Minoru Watanabe, Fuminori Kobayashi: A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL 2006: 1-6
14		Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi: An optically differential reconfigurable gate array with a holographic memory. IPDPS 2006
13		Minoru Watanabe, Fuminori Kobayashi: Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS 2006
	2005
12		Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi: Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT 2005: 287-288
11		Minoru Watanabe, Fuminori Kobayashi: A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT 2005: 297-298
10		Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS 2005
9		Minoru Watanabe, Fuminori Kobayashi: A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) 2005: 1214-1217
8		Minoru Watanabe, Fuminori Kobayashi: An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI 2005: 136-141
7		Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi: Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI 2005: 274-275
	2004
6		Minoru Watanabe, Fuminori Kobayashi: Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA 2004: 299-302
5		Minoru Watanabe, Fuminori Kobayashi: Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA 2004: 311
4		Minoru Watanabe, Fuminori Kobayashi: A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL 2004: 261-269
3		Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design 2004: 735-
	2003
2		Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS 2003: 188
	1995
1		Fuminori Kobayashi, Masayuki Haratsu: A Digital PLL with Finite Impulse Responses. ISCAS 1995: 191-194

Coauthor Index

1	Masayuki Haratsu	[1]
2	Mototsugu Miyano	[7] [12] [14] [18]
3	Rio Miyazaki	[22]
4	Yasuyuki Morikawa	[24]
5	Takenori Shiki	[23]
6	Minoru Watanabe	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]

Colors in the list of coauthors