 | 2008 |
|---|
| 10 |       | Philipp V. Panitz,
Markus Olbrich,
Erich Barke,
Markus Bühler,
Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation.
ACM Great Lakes Symposium on VLSI 2008: 17-22 |
| 2007 |
|---|
| 9 | | Philipp V. Panitz,
Markus Olbrich,
Erich Barke,
Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints.
ACM Great Lakes Symposium on VLSI 2007: 43-48 |
| 2006 |
|---|
| 8 | | Markus Bühler,
Jürgen Koehl,
Jeanne Bickford,
Jason Hibbeler,
Ulf Schlichtmann,
R. Sommer,
Michael Pronath,
Andreas Ripp:
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
DATE 2006: 387-392 |
| 7 | | Jeanne Bickford,
Jason Hibbeler,
Markus Bühler,
Jürgen Koehl,
Dirk Muller,
Sven Peyer,
Christian Schulte:
Yield Improvement by Local Wiring Redundancy.
ISQED 2006: 473-478 |
| 2003 |
|---|
| 6 | | David E. Lackey,
Paul S. Zuchowski,
Jürgen Koehl:
Designing mega-ASICs in nanogate technologies.
DAC 2003: 770-775 |
| 2001 |
|---|
| 5 | | Rob A. Rutenbar,
Olivier Coudert,
Patrick Groeneveld,
Jürgen Koehl,
Scott Peterson,
Vivek Raghavan,
Naresh Soni:
Automatic Hierarchical Design: Fantasy or Reality? (Panel).
ICCAD 2001: 656- |
| 1998 |
|---|
| 4 | | Jürgen Koehl,
Ulrich Baur,
Thomas Ludwig,
Bernhard Kick,
Thomas Pflueger:
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.
DATE 1998: 312-320 |
| 3 | | Tilmann Stöhr,
Markus Alt,
Asmus Hetzel,
Jürgen Koehl:
Analysis, reduction and avoidance of crosstalk on VLSI chips.
ISPD 1998: 211-218 |
| 1997 |
|---|
| 2 | | Bernhard Kick,
Ulrich Baur,
Jürgen Koehl,
Thomas Ludwig,
Thomas Pflueger:
Standard-cell-based design methodology for high-performance support chips.
IBM Journal of Research and Development 41(4&5): 505-514 (1997) |
| 1991 |
|---|
| 1 | | Ren-Song Tsay,
Jürgen Koehl:
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement.
DAC 1991: 620-625 |
