 | 2006 |
|---|
| 10 |       | David Abercrombie,
Bernd Koenemann,
Nagesh Tamarapalli,
Srikanth Venkataraman:
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
VLSI Design 2006: 14 |
| 2004 |
|---|
| 9 | | Bernd Koenemann:
Design/process learning from electrical test.
ICCAD 2004: 733-738 |
| 8 | | Bernd Koenemann:
Test In the Era of "What You see Is NOT What You Get".
ITC 2004: 12 |
| 2003 |
|---|
| 7 | | Bernd Koenemann:
STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data.
Asian Test Symposium 2003: 142-147 |
| 2002 |
|---|
| 6 | | Fidel Muradali,
Mike Ricchetti,
Bart Vermeulen,
Bulent I. Dervisoglu,
Bob Gottlieb,
Bernd Koenemann,
C. J. Clark:
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?
VTS 2002: 445-446 |
| 2001 |
|---|
| 5 | | Bill Bottoms,
Jim Chung,
Bernd Koenemann,
Glenn Shirley,
Lisa Spainhower:
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue.
VTS 2001: 153-154 |
| 2000 |
|---|
| 4 | | John A. Darringer,
Evan E. Davidson,
David J. Hathaway,
Bernd Koenemann,
Mark A. Lavin,
Joseph K. Morrell,
Khalid Rahmat,
Wolfgang Roesner,
Erich C. Schanzenbach,
Gustavo Tellez,
Louise Trevillyan:
EDA in IBM: past, present, and future.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1476-1497 (2000) |
| 1997 |
|---|
| 3 | | D. Cheung,
Bernd Koenemann,
S. Nishtala,
B. West,
D. Wu:
ATE for VLSI: What Challenges Lie Ahead?
VTS 1997: 318-319 |
| 1996 |
|---|
| 2 | | Bernd Koenemann,
J. Monzel,
T. Powell,
N. Saxena,
K. Wagner:
Design Validation: Formal Verification vs. Simulation vs. Functional Testing.
VTS 1996: 364-365 |
| 1 | | Bernd Koenemann,
J. Monzel,
T. Powell,
N. Saxena,
K. Wagner:
BIST: Advantages or Limitations?
VTS 1996: 366-367 |
