| 2009 | ||
|---|---|---|
| 19 | Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach: From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751 | |
| 2008 | ||
| 18 | Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini: ESL hand-off: fact or EDA fiction? DAC 2008: 310-312 | |
| 17 | Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel: Heterogeneous System-level Specification Using SystemC. DATE 2008 | |
| 16 | Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr: SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. IJES 3(3): 109-118 (2008) | |
| 15 | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. IJES 3(3): 150-159 (2008) | |
| 2006 | ||
| 14 | Tim Kogel, Matthew Braun: Virtual prototyping of embedded platforms for wireless and multimedia. DATE 2006: 488-490 | |
| 2005 | ||
| 13 | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel: A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 | |
| 12 | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 | |
| 11 | Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 | |
| 10 | Tim Kogel, Anssi Haverinen: OCP TLM for Architectural Modelling. FDL 2005: 225-244 | |
| 2004 | ||
| 9 | Tim Kogel, Heinrich Meyr: Heterogeneous MP-SoC: the solution to energy-efficient signal processing. DAC 2004: 686-691 | |
| 8 | Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 | |
| 7 | Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 | |
| 6 | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 | |
| 5 | Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 | |
| 2003 | ||
| 4 | Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann: Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. ASAP 2003: 161-171 | |
| 3 | Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 | |
| 2001 | ||
| 2 | Andreas Hoffmann, Tim Kogel, Heinrich Meyr: A framework for fast hardware-software co-simulation. DATE 2001: 760-765 | |
| 1 | Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001) | |