Tetsushi Koide

	2008
46		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Transactions 91-C(9): 1409-1418 (2008)
	2007
45		Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528
44		Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch: Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Transactions 90-A(6): 1240-1243 (2007)
43		Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka: 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Transactions 90-C(11): 2157-2160 (2007)
42		Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Transactions 90-D(1): 334-345 (2007)
41		Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Transactions 90-D(1): 346-354 (2007)
40		Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Transactions 90-D(8): 1312-1315 (2007)
	2006
39		Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300
38		Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch: Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS 2006: 1309-1312
37		Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch: Application of Multi-ported CAM for Parallel Coding. APCCAS 2006: 1859-1862
36		Takashi Morimoto, Hidekazu Adachi, K. Yamaoka, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS 2006: 944-947
35		K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC 2006: 176-181
34		K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch: Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS 2006
33		Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006)
32		Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch: Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Transactions 89-D(3): 1299-1302 (2006)
	2005
31		Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch: A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14
30		Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch: Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) 2005: 3215-3218
29		T. Saito, M. Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, K. Aoyama, Tetsushi Koide, Hans Jürgen Mattausch: Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510
28		Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205
27		Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara: Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Transactions 88-C(4): 622-629 (2005)
26		Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide: A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Transactions 88-C(6): 1332-1342 (2005)
25		Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide: Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems and Computers in Japan 36(9): 1-13 (2005)
	2004
24		Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch: 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC 2004: 531-532
23		Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch: Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544
22		Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka: Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552
	2002
21		Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide: A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33(12): 87-96 (2002)
	2001
20		Tetsushi Koide, S. Shinmori, H. Ishii: Topological optimization with a network reliability constraint. Discrete Applied Mathematics 115(1-3): 135-149 (2001)
19		Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32(1): 29-37 (2001)
	2000
18		Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno: Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10
17		Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi: Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104
	1999
16		Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184
15		Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta: An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40
14		Tetsushi Koide, Shin'ichi Wakabayashi: A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integration 27(1): 57-76 (1999)
	1998
13		Tetsushi Koide, Shin'ichi Wakabayashi: A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583
12		Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide: Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037
	1997
11		Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida: A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integration 24(1): 53-77 (1997)
	1996
10		Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: Pin assignment with global routing for VLSI building block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1575-1583 (1996)
9		Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-the-cell multi-channel router for a new cell model. Integration 21(3): 171-189 (1996)
	1995
8		Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru: A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995
7		Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995
6		Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995
5		Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923
4		Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida: An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214
	1994
3		Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida: A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168
2		Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida: A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228
	1993
1		Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida: Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062

Coauthor Index

1	Md. Anwarul Abedin	[38] [44]
2	Hidekazu Adachi	[30] [31] [32] [34] [35] [36]
3	Ali Ahmadi	[38] [44]
4	Kenji Anami	[27]
5	K. Aoyama	[29]
6	Kazutami Arimoto	[26] [27] [28] [33] [40] [42] [45] [46]
7	K. Awane	[34] [36]
8	Takahiro Deguchi	[17]
9	Katsumi Dosaka	[27] [28] [33] [40] [42] [45] [46]
10	Kazuyasu Fujishima	[27]
11	Mutsuaki Goto	[15]
12	Takayuki Gyohten	[46]
13	Yohmei Harada	[24] [30]
14	Koichi Hatta	[12] [15] [16] [19]
15	Tetsuo Hironaka	[22] [25] [29] [39] [43]
16	Kazunari Inoue	[26] [27]
17	Tomohiro Inoue	[25]
18	H. Ishii	[20]
19	Masakatsu Ishizaki	[37] [40] [41] [42] [46]
20	Kazunori Isomoto	[2]
21	Koh Johguchi	[39] [43]
22	Yoshinori Katsura	[3] [7]
23	Osamu Kiriyama	[30] [31] [32]
24	Yutaka Kono	[41]
25	Y. Kouno	[37]
26	Takeshi Kumaki	[28] [37] [40] [41] [42] [45] [46]
27	Yasuto Kuroda	[28] [40] [42] [45] [46]
28	Hiroshi Kusumoto	[1]
29	M. Maeda	[29]
30	Hans Jürgen Mattausch	[22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46]
31	Hideki Mishima	[1]
32	Yosuke Mitani	[22]
33	Tetsuya Miyoshi	[4]
34	Takashi Morimoto	[24] [30] [31] [32] [34] [35] [36]
35	Fukashi Morishita	[33]
36	Toshihiro Nakaoa	[5]
37	Yoshikatsu Nakayama	[15]
38	Yutaka Nishimaru	[8] [11]
39	Hideyuki Noda	[26] [27] [28] [33] [40] [42] [45] [46]
40	Nobuhiko Omori	[25]
41	Mitsuhiro Ono	[8] [11]
42	Kazunori Saito	[28] [40] [42] [45] [46]
43	T. Saito	[29]
44	Shogo Sakakibara	[44]
45	Takahiro Sasaki	[25]
46	S. Shinmori	[20]
47	Tetsuya Sueyoshi	[22] [29]
48	Masashige Suzuki	[12]
49	Shigeki Takekawa	[21]
50	Yuki Tanaka	[38] [44]
51	Kazuya Tanigawa	[29] [39]
52	Naoyoshi Toshine	[15]
53	Nayoshi Toshine	[18]
54	Masahiro Tsuchiya	[6] [9]
55	Hiroshi Uchida	[22]
56	Hajime Ueno	[18]
57	Shin'ichi Wakabayashi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21]
58	Masataka Yamane	[18]
59	K. Yamaoka	[34] [35] [36]
60	Katsumi Yamatani	[3]
61	Yuji Yano	[23]
62	Noriyoshi Yoshida	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11]
63	Tsutomu Yoshihara	[27]
64	Zhaomin Zhu	[31] [39]

Colors in the list of coauthors