 | 1997 |
|---|
| 3 |       | Raminder Singh Bajwa,
Mitsuru Hiraki,
Hirotsugu Kojima,
Douglas J. Gorny,
Ken-ichi Nitta,
Avadhani Shridhar,
Koichi Seki,
Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. VLSI Syst. 5(4): 417-424 (1997) |
| 1996 |
|---|
| 2 | | Hirotsugu Kojima,
Avadhani Shridhar:
Interlaced accumulation programming for low power DSP.
ISLPED 1996: 213-216 |
| 1 | | Mitsuru Hiraki,
Raminder Singh Bajwa,
Hirotsugu Kojima,
Douglas J. Gorny,
Ken-ichi Nitta,
Avadhani Shridhar,
Katsuro Sasaki,
Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
ISLPED 1996: 353-358 |
