Satoshi Komatsu

	2009
19		Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Transactions 92-A(6): 1464-1475 (2009)
	2007
18		Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satoshi Komatsu, Masahiro Fujita: Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285
17		Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA 2007: 553-563
16		Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134
	2006
15		Satoshi Komatsu, Masahiro Fujita: An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS 2006
14		Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Synchronization Verification in System-Level Design with ILP Solvers. IEICE Transactions 89-A(12): 3387-3396 (2006)
13		Yu Liu, Satoshi Komatsu, Masahiro Fujita: The AMS Extension to System Level Design Language - SpecC. IEICE Transactions 89-A(12): 3397-3407 (2006)
12		Yu Liu, Satoshi Komatsu, Masahiro Fujita: Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Transactions 89-A(4): 1018-1026 (2006)
	2005
11		Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI 2005: 130-133
10		Yu Liu, Satoshi Komatsu, Masahiro Fujita: AMS Extensions for Timed/Untimed System-Level Design Language. FDL 2005: 77-81
9		Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144
8		Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Synchronization verification in system-level design with ILP solvers. MEMOCODE 2005: 121-130
7		Satoshi Komatsu, Masahiro Fujita: Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Transactions 88-A(12): 3282-3289 (2005)
	2003
6		Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima: Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279
5		Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita: Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94
4		Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42
	2002
3		Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108
	1999
2		Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI 1999: 368-371
	1998
1		Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC 1998: 323-324

Coauthor Index

1	Kunihiro Asada	[1] [2] [4]
2	Masahiro Fujita	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
3	Shanghua Gao	[9] [16] [19]
4	Makoto Ikeda	[1] [2] [4]
5	Tohru Ishihara	[4]
6	Y. Ishikawa	[18]
7	Yoshihisa Kojima	[3] [5] [6]
8	Yu Liu	[10] [11] [12] [13]
9	Hiroshi Saito	[3] [5] [6]
10	Thanyapat Sakunkonchak	[6] [8] [11] [14] [17]
11	Kenshu Seto	[3] [5] [6] [9] [16] [18] [19]
12	Shigeru Watanabe	[18]
13	Hiroaki Yoshida	[19]