 | 2007 |
|---|
| 11 |       | Masaki Kataoka,
Akira Koseki,
Hideaki Komatsu,
Yoshiaki Fukazawa:
Non-Retrial Register Allocation and its Spill Optimization Method.
PDPTA 2007: 1047- |
| 2004 |
|---|
| 10 |  | Tamiya Onodera,
Kiyokuni Kawachiya,
Akira Koseki:
Lock Reservation for Java Reconsidered.
ECOOP 2004: 559-583 |
| 9 | | Toshio Suganuma,
Takeshi Ogasawara,
Kiyokuni Kawachiya,
Mikio Takeuchi,
Kazuaki Ishizaki,
Akira Koseki,
Tatsushi Inagaki,
Toshiaki Yasue,
Motohiro Kawahito,
Tamiya Onodera,
Hideaki Komatsu,
Toshio Nakatani:
Evolution of a Java just-in-time compiler for IA-32 platforms.
IBM Journal of Research and Development 48(5-6): 767-796 (2004) |
| 2003 |
|---|
| 8 | | Akira Koseki,
Hideaki Komatsu,
Toshio Nakatani:
Spill Code Minimization by Spill Code Motion.
IEEE PACT 2003: 125-134 |
| 7 | | Kazuaki Ishizaki,
Mikio Takeuchi,
Kiyokuni Kawachiya,
Toshio Suganuma,
Osamu Gohda,
Tatsushi Inagaki,
Akira Koseki,
Kazunori Ogata,
Motohiro Kawahito,
Toshiaki Yasue,
Takeshi Ogasawara,
Tamiya Onodera,
Hideaki Komatsu,
Toshio Nakatani:
Effectiveness of cross-platform optimizations for a java just-in-time compiler.
OOPSLA 2003: 187-204 |
| 2002 |
|---|
| 6 | | Kiyokuni Kawachiya,
Akira Koseki,
Tamiya Onodera:
Lock reservation: Java locks can mostly do without atomic operations.
OOPSLA 2002: 130-141 |
| 5 | | Akira Koseki,
Hideaki Komatsu,
Toshio Nakatani:
Preference-Directed Graph Coloring.
PLDI 2002: 33-44 |
| 1998 |
|---|
| 4 | | Nobuhiro Kondo,
Akira Koseki,
Hideaki Komatsu,
Yoshiaki Fukazawa:
A method for applying loop unrolling and software pipelining to instruction-level parallel architectures.
Systems and Computers in Japan 29(9): 62-73 (1998) |
| 1997 |
|---|
| 3 | | Akira Koseki,
Yoshiaki Fukazawa,
Hideaki Komatsu:
A Register Allocation Technique Using Register Existence Graph.
ICPP 1997: 404-411 |
| 2 | | Akira Koseki,
Hideaki Komatsu,
Yoshiaki Fukazawa:
A method for estimating optimal unrolling times for nested loops.
ISPAN 1997: 376-382 |
| 1996 |
|---|
| 1 | | Akira Koseki,
Hideaki Komatsu,
Yoshiaki Fukazawa:
A Register Allocation Technique Using Guarded PDG.
International Conference on Supercomputing 1996: 270-277 |
