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22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMilan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar: Preface. Electr. Notes Theor. Comput. Sci. 251: 1-3 (2009)
2008
21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLukás Starecek, Lukás Sekanina, Zdenek Kotásek: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Power Conscious RTL Test Scheduling. DSD 2008: 721-728
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMartin Straka, Zdenek Kotásek, Jan Winter: Digital Systems Architectures Based on On-line Checkers. DSD 2008: 81-87
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTomas Pecenka, Lukás Sekanina, Zdenek Kotásek: Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Testability analysis based on the identification of testable blocks with predefined properties. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 296-302 (2008)
2007
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMartin Straka, Jiri Tobola, Zdenek Kotásek: Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT 2007: 152-160
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka: Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679
2006
13no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMatteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 IEEE Computer Society 2006
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193
11no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTomas Pecenka, Zdenek Kotásek, Lukás Sekanina: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289
10no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLukás Sekanina, Lukás Starecek, Zdenek Kotásek: Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina: Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosef Strnadel, Zdenek Kotásek: SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS 2006: 497-498
2005
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosef Strnadel, Zdenek Kotásek: Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD 2005: 420-427
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58
2003
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLZdenek Kotásek, Daniel Mika, Josef Strnadel: Test scheduling for embedded systems. DSD 2003: 463-467
2002
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosef Strnadel, Zdenek Kotásek: Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD 2002: 166-173
1997
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLZdenek Kotásek, F. Zboril: RT level testability analysis to reduce test application time. EUROMICRO 1997: 104-
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJ. Blatný, Zdenek Kotásek, Jan Hlavicka: RT Level Test Scheduling. Computers and Artificial Intelligence 16(1): (1997)
1995
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJ. Blatný, Zdenek Kotásek: I-Path Analysis. Computers and Artificial Intelligence 14(5): (1995)

Coauthor Index

1J. Blatný [1] [2]
2Jiri Bucek [13]
3Milan Ceska [22]
4Zbysek Gajda [12]
5Tomas Herrman [15] [17] [20]
6Jan Hlavicka [2]
7Jan Korenek [14]
8Mojmír Kretínský [22]
9Pavel Kubalík [13]
10Hana Kubatova [13]
11Tomás Martínek [14]
12Ludek Matyska [22]
13Daniel Mika [5]
14Ondrej Novák [13]
15Tomas Pecenka [6] [9] [11] [18]
16Matteo Sonza Reorda [13]
17Lukás Sekanina [6] [9] [10] [11] [12] [18] [21]
18Jaroslav Skarvada [15] [17] [20]
19Lukás Starecek [10] [12] [21]
20Martin Straka [14] [16] [19]
21Bernd Straube [13]
22Josef Strnadel [4] [5] [6] [7] [8] [9]
23Jiri Tobola [14] [16]
24Raimund Ubar [13]
25Tomás Vojnar [22]
26Jan Winter [19]
27F. Zboril [3]

Colors in the list of coauthors

Copyright © Fri Dec 4 16:04:45 2009 by Michael Ley (ley@uni-trier.de)