 | 2008 |
|---|
| 9 |       | Ronny Krashinsky,
Christopher Batten,
Krste Asanovic:
Implementing the scale vector-thread processor.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 2007 |
|---|
| 8 | | Seongmoo Heo,
Ronny Krashinsky,
Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
IEEE Trans. VLSI Syst. 15(9): 1060-1064 (2007) |
| 2005 |
|---|
| 7 | | Ronny Krashinsky,
Hari Balakrishnan:
Minimizing Energy for Wireless Web Access with Bounded Slowdown.
Wireless Networks 11(1-2): 135-148 (2005) |
| 2004 |
|---|
| 6 | | Ronny Krashinsky,
Christopher Batten,
Mark Hampton,
Steve Gerding,
Brian Pharris,
Jared Casper,
Krste Asanovic:
The Vector-Thread Architecture.
ISCA 2004: 52-63 |
| 5 | | Christopher Batten,
Ronny Krashinsky,
Steve Gerding,
Krste Asanovic:
Cache Refill/Access Decoupling for Vector Machines.
MICRO 2004: 331-342 |
| 4 | | Ronny Krashinsky,
Christopher Batten,
Mark Hampton,
Steve Gerding,
Brian Pharris,
Jared Casper,
Krste Asanovic:
The Vector-Thread Architecture.
IEEE Micro 24(6): 84-90 (2004) |
| 2002 |
|---|
| 3 | | Ronny Krashinsky,
Hari Balakrishnan:
Minimizing energy for wireless web access with bounded slowdown.
MOBICOM 2002: 119-130 |
| 2001 |
|---|
| 2 | | Seongmoo Heo,
Ronny Krashinsky,
Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
ARVLSI 2001: 59-74 |
| 1 | | Michael Sung,
Ronny Krashinsky,
Krste Asanovic:
Multithreading decoupled architectures for complexity-effective general purpose computing.
SIGARCH Computer Architecture News 29(5): 56-61 (2001) |
