 | 2007 |
|---|
| 6 |       | Jiun-Ping Wang,
Shiann-Rong Kuang:
Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.
SiPS 2007: 157-162 |
| 2005 |
|---|
| 5 | | Shiann-Rong Kuang,
Chin-Yang Chen,
Ren-Zheng Liao:
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming.
ICPADS (2) 2005: 37-41 |
| 2002 |
|---|
| 4 | | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau,
Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst. 10(6): 924-929 (2002) |
| 1999 |
|---|
| 3 | | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction.
ASP-DAC 1999: 209- |
| 1994 |
|---|
| 2 |  | Jer-Min Jou,
Ren-Der Chen,
Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
ISCAS 1994: 45-48 |
| 1993 |
|---|
| 1 | | Jer-Min Jou,
Shiann-Rong Kuang:
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
ICCD 1993: 379-382 |
