Anshul Kumar

	2009
59		Awadhesh Kumar Singh, Rohit Bhat, Anshul Kumar: An Index-Based Mobile Checkpointing and Recovery Algorithm. ICDCN 2009: 200-205
	2008
58		Nagaraju Pothineni, Anshul Kumar, Kolin Paul: Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. VLSI Design 2008: 261-266
57		Nagaraju Pothineni, Anshul Kumar, Kolin Paul: A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSI Design 2008: 348-353
	2007
56		Nagaraju Pothineni, Anshul Kumar, Kolin Paul: Recurring Pattern Identification and its Application to Instruction Set Extension. CDES 2007: 67-73
55		Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda: Power Reduction in VLIW Processor with Compiler Driven Bypass Network. VLSI Design 2007: 233-238
54		Nagaraju Pothineni, Anshul Kumar, Kolin Paul: Application Specific Datapath Extension with Distributed I/O Functional Units. VLSI Design 2007: 551-558
53		Anup Gangwar, M. Balakrishnan, Anshul Kumar: Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007)
52		Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. International Journal of Parallel Programming 35(6): 507-527 (2007)
	2006
51		Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar: Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46
	2005
50		Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735
49		Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet: Battery Model for Embedded Systems. VLSI Design 2005: 105-110
48		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design 2005: 274-279
	2004
47		Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65
46		Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne: Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32
45		Venkat Rao, Gaurav Singhal, Anshul Kumar: Real Time Dynamic Voltage Scaling For Embedded Systems. VLSI Design 2004: 650-653
44		Sourabh Saluja, Anshul Kumar: Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. VLSI Design 2004: 761-764
43		Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783
42		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP design. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1693-1699 (2004)
	2003
41		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127
40		Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar: Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. VLSI Design 2003: 177-182
39		Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar: SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585-
	2002
38		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP synthesis. CASES 2002: 252-261
37		Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. IEEE International Workshop on Rapid System Prototyping 2002: 66-
36		M. Balakrishnan, Anshul Kumar, C. P. Joshi: A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS 2002: 180-185
35		M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7
34		Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar: Exploring the Number of Register Windows in ASIP Synthesis. VLSI Design 2002: 233-238
33		Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan: A New Divide and Conquer Method for Achieving High Speed Division in Hardware. VLSI Design 2002: 535-540
	2001
32		Anupam Rastogi, M. Balakrishnan, Anshul Kumar: Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design 2001: 23-28
31		Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa: Synthesizing A Long Latency Unit Within Vliw Processor. VLSI Design 2001: 460-
30		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76-
	2000
29		Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. FPL 2000: 201-210
28		Sushil Chandra Jain, Shashi Kumar, Anshul Kumar: Evaluation of Various Routing Architectures for Multi-FPGA Boards. VLSI Design 2000: 262-267
27		Arvind Rajawat, M. Balakrishnan, Anshul Kumar: nterface Synthesis: Issues and Approaches. VLSI Design 2000: 92
26		Johnny Öberg, Anshul Kumar, Ahmed Hemani: Grammar-based hardware synthesis from port-size independent specifications. IEEE Trans. VLSI Syst. 8(2): 184-194 (2000)
25		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A scheme for multiple on-chip signature checking for embedded SRAMS. Journal of Systems Architecture 46(2): 181-199 (2000)
	1999
24		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Built-in Self Test Based on Multiple On-Chip Signature Checking. J. Electronic Testing 14(3): 227-244 (1999)
	1998
23		Johnny Öberg, Ahmed Hemani, Anshul Kumar: Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. DATE 1998: 596-
22		Johnny Öberg, Anshul Kumar, Ahmed Hemani: Specification of Exception Handling in Grammar-Based Hardware Synthesis. EUROMICRO 1998: 10038-10041
21		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Hybrid Testing Schemes Based on Mutual and Signature Testing. VLSI Design 1998: 293-
20		Johnny Öberg, Axel Jantsch, Anshul Kumar: An Object-Oriented Concept for Intelligent Library Functions. VLSI Design 1998: 355-358
19		Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar: Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405
18		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: On-Chip Signature Checking for Embedded Memories. VLSI Design 1998: 558-563
17		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 624-631 (1998)
16		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. J. Electronic Testing 12(3): 199-216 (1998)
	1997
15		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC 1997: 625
14		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139
13		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Efficient Implementation of Multiple On-Chip Signature Checking. VLSI Design 1997: 297-302
	1996
12		Johnny Öberg, Anshul Kumar, Ahmed Hemani: Grammar-Based Hardware Synthesis of Data Communication Protocols. ISSS 1996: 14-19
11		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A Novel BIST Architecture With Built-in Self Check. VLSI Design 1996: 57-60
	1995
10		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148
9		B. M. Subraya, Anshul Kumar, Shashi Kumar: An HOL based framework for design of correct high level synthesizers. VLSI Design 1995: 249-254
8		Alok Kumar, Anshul Kumar, M. Balakrishnan: Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. VLSI Design 1995: 75-80
	1994
7		A. R. Naseer, M. Balakrishnan, Anshul Kumar: An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110
6		A. R. Naseer, M. Balakrishnan, Anshul Kumar: FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24
	1993
5		C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer: High Level Design Experiences with IDEAS. VLSI Design 1993: 110
4		M. V. Rao, M. Balakrishnan, Anshul Kumar: DESSERT: Design Space Exploration of RT Level Components. VLSI Design 1993: 299-304
	1985
3		Kumar Ramayya, Anshul Kumar, Surendra Prasad: An automated data path synthesizer for a canonic structure, implementable in VLSI. DAC 1985: 381-387
2		Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra: Automatic generation of digital system schematic diagrams. DAC 1985: 388-395
	1980
1		Anshul Kumar, P. C. P. Bhatt: A Structured Language for CAD of Digital Systems. ISCA 1980: 308-316

Coauthor Index

1	Mohammed Fadle Abdulla	[11] [13] [15] [16] [18] [21] [24] [25]
2	C. S. Ajay	[5]
3	Anjali Arya	[2]
4	M. Balakrishnan	[4] [5] [6] [7] [8] [10] [14] [17] [19] [27] [30] [32] [33] [34] [35] [36] [38] [39] [41] [42] [43] [47] [48] [50] [51] [52] [53]
5	Rohit Bhat	[59]
6	P. C. P. Bhatt	[1]
7	Vishal P. Bhatt	[34]
8	Natalino G. Busa	[31]
9	Amit Chhabra	[39]
10	Basant Kumar Dwivedi	[39] [43] [47] [51]
11	Jos T. J. van Eijndhoven	[40]
12	Om Prakash Gangwal	[40]
13	Anup Gangwar	[35] [39] [50] [52] [53]
14	Neeraj Goel	[55]
15	Ram Lakhan Gupta	[31]
16	D. Harikrishna	[5]
17	Ahmed Hemani	[12] [22] [23] [26]
18	Paolo Ienne	[35] [46]
19	Diviya Jain	[46]
20	Manoj Kumar Jain	[30] [38] [41] [42] [48]
21	Sitanshu Jain	[19]
22	Sushil Chandra Jain	[28] [29] [37]
23	Axel Jantsch	[20]
24	C. P. Joshi	[36]
25	M. Karunakaran	[5]
26	Arun Kejariwal	[51]
27	Rohini Krishnan	[33] [40]
28	Alok Kumar	[8]
29	Shashi Kumar	[5] [9] [19] [28] [29] [37]
30	Bhuvan Middha	[35]
31	Amit Misra	[2]
32	Murali Mohan	[33]
33	V. Mudgil	[5]
34	A. R. Naseer	[5] [6] [7] [10] [14] [17]
35	Nicolas Navet	[49]
36	Johnny Öberg	[12] [20] [22] [23] [26]
37	Preeti Ranjan Panda	[50] [52] [55]
38	Kolin Paul	[54] [56] [57] [58]
39	Nagaraju Pothineni	[54] [56] [57] [58]
40	Laura Pozzi	[46]
41	Surendra Prasad	[3]
42	Arvind Rajawat	[27]
43	Kumar Ramayya	[3]
44	M. V. Rao	[4]
45	Venkat Rao	[45] [49]
46	Anupam Rastogi	[32]
47	C. P. Ravikumar	[11] [13] [15] [16] [18] [21] [24] [25]
48	Sourabh Saluja	[44]
49	Awadhesh Kumar Singh	[59]
50	Amarjeet Singh	[39]
51	Gaurav Singhal	[45] [49]
52	B. M. Subraya	[9]
53	V. V. Swaminathan	[2]
54	Aalbert Van Der Werf	[31]

Colors in the list of coauthors