 | 2008 |
|---|
| 6 |       | Kenta Yamada,
Takashi Sato,
Shuhei Amakawa,
Noriaki Nakayama,
Kazuya Masu,
Shigetaka Kumashiro:
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Transactions 91-C(7): 1142-1150 (2008) |
| 5 | | Tatsuya Ezaki,
Dondee Navarro,
Youichi Takeda,
Norio Sadachika,
G. Suzuki,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Takahiro Iizuka,
Masahiko Taguchi,
Shigetaka Kumashiro,
Shunsuke Miyamoto:
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations.
Mathematics and Computers in Simulation 79(4): 1096-1106 (2008) |
| 2005 |
|---|
| 4 | | Shizunori Matsumoto,
Hiroaki Ueno,
Satoshi Hosokawa,
Toshihiko Kitamura,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Transactions 88-C(2): 247-254 (2005) |
| 3 | | Dondee Navarro,
Takeshi Mizoguchi,
Masami Suetake,
Kazuya Hisamitsu,
Hiroaki Ueno,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Transactions 88-C(5): 1079-1086 (2005) |
| 2001 |
|---|
| 2 | | D. Miyawaki,
Shizunori Matsumoto,
Hans Jürgen Mattausch,
S. Ooshiro,
Masami Suetake,
Michiko Miura-Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
ASP-DAC 2001: 39-44 |
| 1993 |
|---|
| 1 | | Shigetaka Kumashiro,
Ronald A. Rohrer,
Andrzej J. Strojwas:
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 988-996 (1993) |
