Ohsang Kwon Coauthor index DBLP Vis pubzone.org

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DBLP keys2002
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOhsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.: A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. VLSI Signal Processing 31(2): 77-89 (2002)
2001
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOhsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka: A fast hybrid carry-lookahead/carry-select adder design. ACM Great Lakes Symposium on VLSI 2001: 149-152
2000
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOhsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka: A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. ASAP 2000: 235-
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLStephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia: "Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717

Coauthor Index

1N. Aoki [1]
2David Boerstler [1]
3P. Coulman [1]
4Sang H. Dhong [1]
5Brian K. Flachs [1]
6H. Peter Hofstee [1]
7N. Kojima [1]
8K. Lee [1]
9D. Meltzer [1]
10Kevin J. Nowka [1] [2] [3] [4]
11J. Park [1]
12J. Peter [1]
13Stephen D. Posluszny [1]
14Joel Silberman [1]
15Earl E. Swartzlander Jr. [2] [3] [4]
16Osamu Takahashi [1]
17Paul G. Villarrubia (Paul Villarrubia) [1]

Copyright © Fri Dec 18 14:20:30 2009 by Michael Ley (ley@uni-trier.de)