 | 2009 |
|---|
| 9 |       | Josefa Díaz,
José Ignacio Hidalgo,
Francisco Fernández,
Oscar Garnica,
Sonia López:
Improving SMT performance: an application of genetic algorithms to configure resizable caches.
GECCO (Companion) 2009: 2029-2034 |
| 2007 |
|---|
| 8 | | Sonia López,
Steve Dropsho,
David H. Albonesi,
Oscar Garnica,
Juan Lanchares:
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.
HiPEAC 2007: 136-150 |
| 7 | | Sonia López,
Steven G. Dropsho,
David H. Albonesi,
Oscar Garnica,
Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.
PACT 2007: 416 |
| 2006 |
|---|
| 6 | | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
DSD 2006: 423-432 |
| 5 | | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.
Euro-Par 2006: 495-505 |
| 4 | | Guadalupe Miñana,
José Ignacio Hidalgo,
Oscar Garnica,
Juan Lanchares,
José Manuel Colmenar,
Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.
PATMOS 2006: 514-523 |
| 2004 |
|---|
| 3 | | Sonia López,
Oscar Garnica,
José Manuel Colmenar:
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.
PATMOS 2004: 623-632 |
| 2 | | José Manuel Colmenar,
Oscar Garnica,
Sonia López,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.
PDP 2004: 112-119 |
| 2003 |
|---|
| 1 | | Sonia López,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.
PATMOS 2003: 151-160 |
