Hung Chi Lai

	1989
6		Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney: The Transduction Method-Design of Logic Networks Based on Permissible Functions. IEEE Trans. Computers 38(10): 1404-1424 (1989)
	1988
5		Hung Chi Lai, Saburo Muroga: Design of MOS networks in single-rail input logic for incompletely specified functions. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 339-345 (1988)
	1987
4		Hung Chi Lai, Saburo Muroga: Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. IEEE Trans. Computers 36(2): 157-166 (1987)
	1982
3		Hung Chi Lai, Saburo Muroga: Logic Networks of Carry-Save Adders. IEEE Trans. Computers 31(9): 870-882 (1982)
	1979
2		Hung Chi Lai, Saburo Muroga: Minimum Parallel Binary Adders with NOR (NAND) Gates. IEEE Trans. Computers 28(9): 648-659 (1979)
	1976
1		Saburo Muroga, Hung Chi Lai: Minimization of Logic Networks Under a Generalized Cost Function. IEEE Trans. Computers 25(9): 893-907 (1976)

Coauthor Index

1	Jay Niel Culliney	[6]
2	Yahiko Kambayashi	[6]
3	Saburo Muroga	[1] [2] [3] [4] [5] [6]