David L. Landis

	2003
20		Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis: Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127
19		David L. Landis, James T. Cain: Microelectronics Education As Workforce Development. MSE 2003: 37-38
18		Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis: The Sandbox Design Experience Course. MSE 2003: 39-40
	2000
17		Bassam Shaer, Sami A. Al-Arian, David L. Landis: Partitioning sequential circuits for pseudoexhaustive testing. IEEE Trans. VLSI Syst. 8(5): 534-541 (2000)
16		Bassam Shaer, David L. Landis, Sami A. Al-Arian: Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits. IEEE Trans. VLSI Syst. 8(6): 750-754 (2000)
	1999
15		Bassam Shaer, Sami A. Al-Arian, David L. Landis: Pseudo-Exhaustive Testing of Sequential Circuits. Great Lakes Symposium on VLSI 1999: 109-
14		David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor: Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. ICCD 1999: 146-151
13		Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian: A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. IEEE International Workshop on Rapid System Prototyping 1999: 222-
12		David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor: Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. IEEE International Workshop on Rapid System Prototyping 1999: 52-
11		David L. Landis: Using RASSP Modules in a Rapid System Prototyping Class. MSE 1999: 53-54
10		Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno: Computing in Memory Architectures for Digital Image Processing. MTDT 1999: 8-15
	1998
9		Bassam Shaer, Sami A. Al-Arian, David L. Landis: Partitioning algorithm to enhance VLSI testability. ACM Southeast Regional Conference 1998: 121-129
	1996
8		Stephan P. Athan, David L. Landis, Sami A. Al-Arian: A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs. VTS 1996: 118-123
	1992
7		David L. Landis, Chuck Hudson, Patrick F. McHugh: Applications of the IEEE P1149.5 Module Test and Maintenance Bus. ITC 1992: 984-992
6		David L. Landis, Nitin Nigam, Joseph W. Yoder: Wafer-Scale Optimization Using Computational Availability. IEEE Computer 25(4): 66-71 (1992)
5		David L. Landis: A test methodology for wafer scale system. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 76-82 (1992)
	1991
4		Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, D. Whittaker: Wafer Scale Integration: A university perspective. VLSI Signal Processing 2(4): 253-269 (1991)
	1989
3		David L. Landis: A Self-Test System Architecture for Reconfigurable WSI. ITC 1989: 275-282
	1988
2		David L. Landis, Daniel C. Muha: Evaluation of System BIST Using Computational Performance Measures. ITC 1988: 531-536
	1987
1		David L. Landis, Daniel C. Muha, William A. Check: Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors. ICPP 1987: 114-116

Coauthor Index

1	Sami A. Al-Arian	[8] [9] [15] [16] [17]
2	Stephan P. Athan	[8]
3	Sanjay Balasubramanian	[13]
4	James T. Cain	[19]
5	Tom Cain	[20]
6	William A. Check	[1]
7	Donald M. Chiarulli	[20]
8	Bruce R. Childers	[20]
9	Lee D. Coraor	[10] [12] [14]
10	Scott Deno	[10] [13] [14]
11	Praveen Guddeti	[12]
12	Raymond R. Hoare (Raymond Hoare)	[20]
13	Chuck Hudson	[7]
14	Paul T. Hulina	[10] [12] [13] [14]
15	Vijay K. Jain	[4]
16	David C. Keezer	[4]
17	Max Khusid	[18]
18	Ivan S. Kourtev	[18] [20]
19	Thomas Kroll	[18]
20	Steven P. Levitan	[20]
21	Patrick F. McHugh	[7]
22	Daniel C. Muha	[1] [2]
23	Nitin Nigam	[6]
24	Luke Roth	[10] [14]
25	Herman Schmit	[18]
26	Bassam Shaer	[9] [15] [16] [17]
27	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[18]
28	D. Whittaker	[4]
29	K. T. Wilson	[4]
30	Joseph W. Yoder	[6]

Colors in the list of coauthors