Pepijn J. de Langen

	2009
7		Pepijn J. de Langen, Ben H. H. Juurlink: Limiting the number of dirty cache lines. DATE 2009: 670-675
6		Pepijn J. de Langen, Ben H. H. Juurlink: Leakage-Aware Multiprocessor Scheduling. Signal Processing Systems 57(1): 73-88 (2009)
	2008
5		Pepijn J. de Langen, Ben H. H. Juurlink: Memory copies in multi-level memory systems. ASAP 2008: 281-286
	2007
4		Pepijn J. de Langen, Ben H. H. Juurlink: Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors. SAMOS 2007: 75-85
	2006
3		Pepijn J. de Langen, Ben H. H. Juurlink: Leakage-aware multiprocessor scheduling for low power. IPDPS 2006
	2004
2		Ben H. H. Juurlink, Pepijn J. de Langen: Dynamic techniques to reduce memory traffic in embedded systems. Conf. Computing Frontiers 2004: 192-201
1		Pepijn J. de Langen, Ben H. H. Juurlink: Reducing traffic generated by conflict misses in caches. Conf. Computing Frontiers 2004: 235-239

Coauthor Index

1

Ben H. H. Juurlink

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