Tracy Larrabee

	2002
22		David B. Lavo, Ismed Hartanto, Tracy Larrabee: Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis. ITC 2002: 250-259
	2001
21		David B. Lavo, Tracy Larrabee: Making cause-effect cost effective: low-resolution fault dictionaries. ITC 2001: 278-286
20		Tracy Larrabee, Jon Colbum: Yield Optimization and Its Relation to Test. VTS 2001: 281-282
	2000
19		Mark J. Boyd, Tracy Larrabee: A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. FCCM 2000: 13-21
	1999
18		David B. Lavo, Tracy Larrabee, Jonathon E. Colburn: Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis. ITC 1999: 1065-1072
17		Brian Chess, Tracy Larrabee: Creating small fault dictionaries [logic circuit fault diagnosis]. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 346-356 (1999)
	1998
16		David B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto: Probabilistic mixed-model fault diagnosis. ITC 1998: 1084-1093
15		Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess: On applying non-classical defect models to automated diagnosis. ITC 1998: 748-757
14		Douglas Williams, F. Joel Ferguson, Tracy Larrabee: A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. VTS 1998: 274-282
13		Brian Chess, Tracy Larrabee: Logic Testing of Bridging Faults in CMOS Integrated Circuits. IEEE Trans. Computers 47(3): 338-345 (1998)
12		David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson: Diagnosing realistic bridging faults with single stuck-at information. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 255-268 (1998)
	1997
11		David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler: Bridging Fault Diagnosis in the Absence of Physical Information. ITC 1997: 887-893
	1996
10		David B. Lavo, Tracy Larrabee, Brian Chess: Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis. ITC 1996: 611-619
9		Haluk Konuk, F. Joel Ferguson, Tracy Larrabee: Charge-based fault simulation for CMOS network breaks. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1555-1567 (1996)
	1995
8		Haluk Konuk, F. Joel Ferguson, Tracy Larrabee: Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. DAC 1995: 345-351
7		Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee: Diagnosis of realistic bridging faults with single stuck-at information. ICCAD 1995: 185-192
	1994
6		Brian Chess, Tracy Larrabee: Generating Test Patterns for Bridge Faults in CMOS ICs. EDAC-ETC-EUROASIC 1994: 165-170
5		Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee: Testing CMOS Logic Gates for Realistic Shorts. ITC 1994: 395-402
	1993
4		Brian Chess, Tracy Larrabee: Bridge Fault simulation strategies for CMOS integrated Circuits. DAC 1993: 458-462
	1992
3		Tracy Larrabee: Test pattern generation using Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 4-15 (1992)
	1991
2		F. Joel Ferguson, Tracy Larrabee: Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. ITC 1991: 492-499
	1989
1		Tracy Larrabee: Efficient Generation of Test Patterns Using Boolean Difference. ITC 1989: 795-802

Coauthor Index

1	Hari Balachandran	[15]
2	Mark J. Boyd	[19]
3	Kenneth M. Butler	[11] [15]
4	Brian Chess	[4] [5] [6] [7] [10] [11] [12] [13] [15] [16] [17]
5	Jon Colbum	[20]
6	Jonathon E. Colburn	[18]
7	F. Joel Ferguson	[2] [5] [7] [8] [9] [11] [12] [14] [15]
8	Anthony Freitas	[5]
9	Ismed Hartanto	[16] [22]
10	Haluk Konuk	[8] [9]
11	David B. Lavo	[7] [10] [11] [12] [15] [16] [18] [21] [22]
12	Jayashree Saxena	[11] [15]
13	Douglas Williams	[14]

Colors in the list of coauthors