| 1999 | ||
|---|---|---|
| 1 | Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim: Reduced Latency IEEE Floating-Point Standard Adder Architectures. IEEE Symposium on Computer Arithmetic 1999: 35- | |
| 1 | Andrew Beaumont-Smith | [1] |
| 2 | Neil Burgess | [1] |
| 3 | Cheng-Chew Lim | [1] |