 | 2009 |
|---|
| 4 |       | Jie Zhou,
Yong Dou,
Jianxun Zhao,
Fei Xia,
Yuanwu Lei,
Yuxing Tang:
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.
APPT 2009: 110-122 |
| 2008 |
|---|
| 3 | | Jie Zhou,
Yong Dou,
Yuanwu Lei,
Yazhuo Dong:
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
ARC 2008: 254-259 |
| 2 | | Jie Zhou,
Yong Dou,
Yuanwu Lei,
Jinbo Xu,
Yazhuo Dong:
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
HPCC 2008: 182-189 |
| 2007 |
|---|
| 1 | | Yong Dou,
Jie Zhou,
Yuanwu Lei,
Xingming Zhou:
FPGA SAR Processor with Window Memory Accesses.
ASAP 2007: 95-100 |
