 | 2008 |
| 35 |  | Fei Wang,
Yu Hu,
Huawei Li,
Xiaowei Li:
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.
ASP-DAC 2008: 571-576 |
| 34 |  | Xiang Fu,
Huawei Li,
Yu Hu,
Xiaowei Li:
Robust test generation for power supply noise induced path delay faults.
ASP-DAC 2008: 659-662 |
| 33 |  | Da Wang,
Rui Li,
Yu Hu,
Huawei Li,
Xiaowei Li:
A Case Study on At-Speed Testing for a Gigahertz Microprocessor.
DELTA 2008: 326-331 |
| 32 |  | Minjin Zhang,
Huawei Li,
Xiaowei Li:
Static Crosstalk Noise Analysis with Transition Map.
DELTA 2008: 462-465 |
| 31 |  | Hui Liu,
Huawei Li,
Yu Hu,
Xiaowei Li:
A Scan-Based Delay Test Method for Reduction of Overtesting.
DELTA 2008: 521-526 |
| 30 |  | Ying Zhang,
Huawei Li,
Xiaowei Li,
Yu Hu:
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.
VTS 2008: 377-382 |
| 29 |  | Minjin Zhang,
Huawei Li,
Xiaowei Li:
Multiple Coupling Effects Oriented Path Delay Test Generation.
VTS 2008: 383-388 |
| 28 |  | Da Wang,
Yu Hu,
Huawei Li,
Xiaowei Li:
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.
J. Comput. Sci. Technol. 23(6): 1037-1046 (2008) |
| 2007 |
| 27 |  | Lei Zhang,
Huawei Li,
Xiaowei Li:
A Routing Algorithm for Random Error Tolerance in Network-on-Chip.
HCI (4) 2007: 1210-1219 |
| 26 |  | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) |
| 2006 |
| 25 |  | Huawei Li,
Yu Fan,
Tao Wu:
Impact of Load Characteristics and Low-Voltage Load Shedding Schedule on Dynamic Voltage Stability.
CCECE 2006: 2249-2252 |
| 24 |  | Huawei Li,
Yu Fan,
Rong Shi:
Chaos and Ferroresonance.
CCECE 2006: 494-497 |
| 23 |  | Tong Liu,
Huawei Li,
Xiaowei Li,
Yinhe Han:
Fast Packet Classification using Group Bit Vector.
GLOBECOM 2006 |
| 22 |  | Huawei Li,
Pei-Fu Shen,
Xiaowei Li:
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.
VTS 2006: 300-305 |
| 21 |  | Yu Hu,
Yinhe Han,
Xiaowei Li,
Huawei Li,
Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions 89-D(10): 2616-2625 (2006) |
| 20 |  | Yinhe Han,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences 49(2): 262-272 (2006) |
| 2005 |
| 19 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
ASP-DAC 2005: 53-58 |
| 18 |  | Shuguang Gong,
Huawei Li,
Yufeng Xu,
Tong Liu,
Xiaowei Li:
Design of an efficient memory subsystem for network processor.
ASP-DAC 2005: 897-900 |
| 17 |  | Pei-Fu Shen,
Huawei Li,
Yongjun Xu,
Xiaowei Li:
Non-robust Test Generation for Crosstalk-Induced Delay Faults.
Asian Test Symposium 2005: 120-125 |
| 16 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains.
ISQED 2005: 238-243 |
| 15 |  | Yu Hu,
Xiaowei Li,
Huawei Li,
Xiaoqing Wen:
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
PRDC 2005: 175-182 |
| 14 |  | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra,
Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions 88-D(9): 2126-2134 (2005) |
| 13 |  | Yinhe Han,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol. 20(2): 201-209 (2005) |
| 12 |  | Huawei Li,
Xiaowei Li:
Selection of Crosstalk-Induced Faults in Enhanced Delay Test.
J. Electronic Testing 21(2): 181-195 (2005) |
| 2004 |
| 11 |  | Yu Hu,
Yinhe Han,
Huawei Li,
Tao Lv,
Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs.
Asian Test Symposium 2004: 236-241 |
| 10 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores.
Asian Test Symposium 2004: 8-13 |
| 9 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
DFT 2004: 298-305 |
| 2003 |
| 8 |  | Huawei Li,
Yue Zhang,
Xiaowei Li:
Delay Test Pattern Generation Considering Crosstalk-Induced Effects.
Asian Test Symposium 2003: 178-183 |
| 7 |  | Yinhe Han,
Yongjun Xu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Asian Test Symposium 2003: 440-445 |
| 6 |  | Zhigang Yin,
Yinghua Min,
Xiaowei Li,
Huawei Li:
A Novel RT-Level Behavioral Description Based ATPG Method.
J. Comput. Sci. Technol. 18(3): 308-317 (2003) |
| 2002 |
| 5 |  | Zuying Luo,
Xiaowei Li,
Huawei Li,
Shiyuan Yang,
Yinghua Min:
Test Power Optimization Techniques for CMOS Circuits.
Asian Test Symposium 2002: 332-337 |
| 2001 |
| 4 |  | Huawei Li,
Yinghua Min,
Zhongcheng Li:
An RT-Level ATPG Based on Clustering of Circuit States.
Asian Test Symposium 2001: 213-218 |
| 3 |  | Xiaowei Li,
Huawei Li,
Yinghua Min:
Reducing Power Dissipation during At-Speed Test Application.
DFT 2001: 116- |
| 2000 |
| 2 |  | Huawei Li,
Zhongcheng Li,
Yinghua Min:
Reduction of Number of Paths to be Tested in Delay Testing.
J. Electronic Testing 16(5): 477-485 (2000) |
| 1998 |
| 1 |  | Huawei Li,
Zhongcheng Li,
Yinghua Min:
Delay Testing with Double Observations.
Asian Test Symposium 1998: 96- |