| 2009 | ||
|---|---|---|
| 78 | Guihai Yan, Yinhe Han, Xiaowei Li: A unified online Fault Detection scheme via checking of Stability Violation. DATE 2009: 496-501 | |
| 2008 | ||
| 77 | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li: A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC 2008: 571-576 | |
| 76 | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: On reducing both shift and capture power for scan-based testing. ASP-DAC 2008: 653-658 | |
| 75 | Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li: Robust test generation for power supply noise induced path delay faults. ASP-DAC 2008: 659-662 | |
| 74 | Changchang Wu, Brian Clipp, Xiaowei Li, Jan-Michael Frahm, Marc Pollefeys: 3D model matching with Viewpoint-Invariant Patches (VIP). CVPR 2008 | |
| 73 | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. DATE 2008: 1184-1189 | |
| 72 | Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li: Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. DATE 2008: 891-896 | |
| 71 | Fei Wang, Yu Hu, Xiaowei Li: Adaptive Diagnostic Pattern Generation for Scan Chains. DELTA 2008: 129-132 | |
| 70 | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. DELTA 2008: 26-31 | |
| 69 | Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li: A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA 2008: 326-331 | |
| 68 | Minjin Zhang, Huawei Li, Xiaowei Li: Static Crosstalk Noise Analysis with Transition Map. DELTA 2008: 462-465 | |
| 67 | Hui Liu, Huawei Li, Yu Hu, Xiaowei Li: A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA 2008: 521-526 | |
| 66 | Xiaowei Li, Changchang Wu, Christopher Zach, Svetlana Lazebnik, Jan-Michael Frahm: Modeling and Recognition of Landmark Image Collections Using Iconic Scene Graphs. ECCV (1) 2008: 427-440 | |
| 65 | Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu: On capture power-aware test data compression for scan-based testing. ICCAD 2008: 67-72 | |
| 64 | Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu: Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS 2008: 377-382 | |
| 63 | Minjin Zhang, Huawei Li, Xiaowei Li: Multiple Coupling Effects Oriented Path Delay Test Generation. VTS 2008: 383-388 | |
| 62 | Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu: BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission. IEICE Transactions 91-C(10): 1690-1697 (2008) | |
| 61 | Da Wang, Yu Hu, Huawei Li, Xiaowei Li: Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23(6): 1037-1046 (2008) | |
| 2007 | ||
| 60 | Lei Zhang, Huawei Li, Xiaowei Li: A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) 2007: 1210-1219 | |
| 59 | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) | |
| 58 | Guangyan Huang, Xiaowei Li, Jing He, Xin Li: Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks. International Journal of Information Technology and Decision Making 6(2): 235-251 (2007) | |
| 57 | Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang: Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. J. Comput. Sci. Technol. 22(5): 673-680 (2007) | |
| 2006 | ||
| 56 | Hongyang Chen, Ping Deng, Yongjun Xu, Xiaowei Li: A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks. APWeb Workshops 2006: 315-320 | |
| 55 | Lei Xie, Yongjun Xu, Xiaowei Li, Yuefei Zhu: A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks. CIT 2006: 229 | |
| 54 | Dan Hou, Xia Shen, Xiaowei Li, Yue Liu, Yongtian Wang: Digital Restoration of Historical Heritage by Reconstruction from Uncalibrated Images. Edutainment 2006: 1377-1382 | |
| 53 | Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han: Fast Packet Classification using Group Bit Vector. GLOBECOM 2006 | |
| 52 | Jie Don, Yu Hu, Yinhe Han, Xiaowei Li: An on-chip combinational decompressor for reducing test data volume. ISCAS 2006 | |
| 51 | Guangyan Huang, Xiaowei Li, Jing He: Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime. International Conference on Computational Science (2) 2006: 1069-1072 | |
| 50 | Huawei Li, Pei-Fu Shen, Xiaowei Li: Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS 2006: 300-305 | |
| 49 | Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006) | |
| 48 | Tao Lv, Jianping Fan, Xiaowei Li, Ling-Yi Liu: Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. J. Electronic Testing 22(3): 273-285 (2006) | |
| 47 | Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra: Response compaction for system-on-a-chip based on advanced convolutional codes. Science in China Series F: Information Sciences 49(2): 262-272 (2006) | |
| 2005 | ||
| 46 | Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li: Vector extraction for average total power estimation. ASP-DAC 2005: 1086-1089 | |
| 45 | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58 | |
| 44 | Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li: Design of an efficient memory subsystem for network processor. ASP-DAC 2005: 897-900 | |
| 43 | Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li: Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium 2005: 120-125 | |
| 42 | Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra: Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium 2005: 372-377 | |
| 41 | Guangmei Zhang, Chen Rui, Xiaowei Li, Han Congying: The Automatic Generation of Basis Set of Path for Path Testing. Asian Test Symposium 2005: 46-51 | |
| 40 | Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong: A State Machine for Detecting C/C++ Memory Faults. Asian Test Symposium 2005: 82-87 | |
| 39 | Xiaowei Li, Yue Liu, Yongtian Wang, Dayuan Yan, Dongdong Weng, Tao Yang: An Improved Colored-Marker Based Registration Method for AR Applications. ICCSA (3) 2005: 266-273 | |
| 38 | Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen: Validation analysis and test flow optimization of VLSI chip. ISCAS (6) 2005: 5666-5669 | |
| 37 | Ji Li, Yinhe Han, Xiaowei Li: Deterministic and low power BIST based on scan slice overlapping. ISCAS (6) 2005: 5670-5673 | |
| 36 | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243 | |
| 35 | Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 | |
| 34 | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005) | |
| 33 | Xiaowei Li, Guanghui Li, Ming Shao: Formal Verification Techniques Based on Boolean Satisfiability Problem. J. Comput. Sci. Technol. 20(1): 38-47 (2005) | |
| 32 | Xiaowei Li: Perface. J. Comput. Sci. Technol. 20(2): 145-145 (2005) | |
| 31 | Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005) | |
| 30 | Huawei Li, Xiaowei Li: Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electronic Testing 21(2): 181-195 (2005) | |
| 2004 | ||
| 29 | Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li: Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 | |
| 28 | Guanghui Li, Xiaowei Li: Circuit-Width Based Heuristic for Boolean Reasoning. Asian Test Symposium 2004: 336-341 | |
| 27 | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 | |
| 26 | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 | |
| 25 | Yinhe Han, Xiaowei Li: Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. ESA/VLSI 2004: 374-381 | |
| 24 | Yongjun Xu, Zuying Luo, Xiaowei Li: A maximum total leakage current estimation method. ISCAS (2) 2004: 757-760 | |
| 23 | Xiaowei Li: Conference Reports. IEEE Design & Test of Computers 21(1): 68- (2004) | |
| 22 | Yongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong: Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. 19(5): 708-717 (2004) | |
| 2003 | ||
| 21 | Yunzhan Gong, Wanli Xu, Xiaowei Li: An Expression's Single Fault Model and the Testing Methods. Asian Test Symposium 2003: 110-115 | |
| 20 | Tao Lv, Jianping Fan, Xiaowei Li: An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. Asian Test Symposium 2003: 161-167 | |
| 19 | Huawei Li, Yue Zhang, Xiaowei Li: Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium 2003: 178-183 | |
| 18 | Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li: Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. Asian Test Symposium 2003: 196-201 | |
| 17 | Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445 | |
| 16 | Guanghui Li, Ming Shao, Xiaowei Li: Design Error Diagnosis Based on Verification Techniques. Asian Test Symposium 2003: 474-477 | |
| 15 | Ming Shao, Guanghui Li, Xiaowei Li: SAT-Based Algorithm of Verification for Port Order Fault. Asian Test Symposium 2003: 478-481 | |
| 14 | Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li: A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. 18(3): 308-317 (2003) | |
| 2002 | ||
| 13 | Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min: Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium 2002: 332-337 | |
| 2001 | ||
| 12 | Zhigang Yin, Yinghua Min, Xiaowei Li: An Approach to RTL Fault Extraction and Test Generation. Asian Test Symposium 2001: 219-224 | |
| 11 | Xiaowei Li, Huawei Li, Yinghua Min: Reducing Power Dissipation during At-Speed Test Application. DFT 2001: 116- | |
| 10 | Xiaowei Li, Paul Y. S. Cheung: A Loop-Based Apparatus for At-Speed Self-Testing. J. Comput. Sci. Technol. 16(3): 278-285 (2001) | |
| 2000 | ||
| 9 | Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara: Strong self-testability for data paths high-level synthesis. Asian Test Symposium 2000: 229-234 | |
| 8 | Xiaowei Li, Paul Y. S. Cheung: High Level Synthesis for Loop-Based BIST. J. Comput. Sci. Technol. 15(4): 338-345 (2000) | |
| 7 | Xiaowei Li, Paul Y. S. Cheung: Exploiting Deterministic TPG for Path Delay Testing. J. Comput. Sci. Technol. 15(5): 472-479 (2000) | |
| 6 | Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara: LFSR-Based Deterministic TPG for Two-Pattern Testing. J. Electronic Testing 16(5): 419-426 (2000) | |
| 1999 | ||
| 5 | Xiaowei Li, Paul Y. S. Cheung: Data Path Synthesis for BIST with Low Area Overhead. ASP-DAC 1999: 275-278 | |
| 4 | Xiaowei Li, Paul Y. S. Cheung: Exploiting Test Resource Optimization in Data Path Synthesis for BIST. Great Lakes Symposium on VLSI 1999: 342-343 | |
| 3 | Xiaowei Li, Paul Y. S. Cheung: An approach to behavioral synthesis for loop-based BIST. ISCAS (6) 1999: 374-377 | |
| 1998 | ||
| 2 | Xiaowei Li, Paul Y. S. Cheung: Exploiting BIST Approach for Two-Pattern Testing. Asian Test Symposium 1998: 424-429 | |
| 1 | Xiaowei Li, Paul Y. S. Cheung: High-Level BIST Synthesis for Delay Testing. DFT 1998: 318- | |