 | 2009 |
|---|
| 4 |       | Bangli Liang,
Zhigong Wang,
Dianyong Chen,
Bo Wang,
Guohui Situ,
Tad Kwasniewski:
A full-rate truly monolithic CMOS CDR for low-cost applications.
CCECE 2009: 1208-1212 |
| 3 | | Dianyong Chen,
Bo Wang,
Bangli Liang,
Tad Kwasniewski:
A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously.
CCECE 2009: 1213-1216 |
| 2 | | Bo Wang,
Dianyong Chen,
Bangli Liang,
Jinguang Jiang,
Tad Kwasniewski:
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel.
CCECE 2009: 1221-1226 |
| 2008 |
|---|
| 1 | | Bangli Liang,
Tad Kwasniewski,
Dianyong Chen:
A 42-Gb/s Decision Circuit in 0.13µm CMOS.
CNSR 2008: 339-342 |
