 | 2009 |
|---|
| 10 |       | Guihai Yan,
Yinhe Han,
Hui Liu,
Xiaoyao Liang,
Xiaowei Li:
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.
ISLPED 2009: 395-400 |
| 2008 |
|---|
| 9 | | Xiaoyao Liang,
Gu-Yeon Wei,
David Brooks:
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.
ISCA 2008: 191-202 |
| 8 | | Gu-Yeon Wei,
David Brooks,
Ali Durlov Khan,
Xiaoyao Liang:
Instruction-driven clock scheduling with glitch mitigation.
ISLPED 2008: 357-362 |
| 7 | | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
IEEE Micro 28(1): 60-68 (2008) |
| 2007 |
|---|
| 6 | | Xiaoyao Liang,
Kerem Turgay,
David Brooks:
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques.
ICCAD 2007: 824-830 |
| 5 | | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Process Variation Tolerant 3T1D-Based Cache Architectures.
MICRO 2007: 15-26 |
| 2006 |
|---|
| 4 | | Xiaoyao Liang,
David Brooks:
Microarchitecture parameter selection to optimize system performance under process variation.
ICCAD 2006: 429-436 |
| 3 | | Xiaoyao Liang,
David Brooks:
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units.
MICRO 2006: 504-514 |
| 2005 |
|---|
| 2 | | Xiaoyao Liang,
Akshay Athalye,
Sangjin Hong:
Equalizing data-path for processing speed determination in block level pipelining.
ISCAS (2) 2005: 1646-1649 |
| 1 | | Xiaoyao Liang,
Akshay Athalye,
Sangjin Hong:
Dynamic coarse grain dataflow reconfiguration technique for real-time systems design.
ISCAS (4) 2005: 3511-3514 |
