 | 2009 |
|---|
| 11 |       | Hongzhong Zheng,
Jiang Lin,
Zhao Zhang,
Zhichun Zhu:
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.
ISCA 2009: 255-266 |
| 10 | | Jiang Lin,
Qingda Lu,
Xiaoning Ding,
Zhao Zhang,
Xiaodong Zhang,
P. Sadayappan:
Enabling software management for multicore caches with a lightweight hardware support.
SC 2009 |
| 2008 |
|---|
| 9 | | Jiang Lin,
Qingda Lu,
Xiaoning Ding,
Zhao Zhang,
Xiaodong Zhang,
P. Sadayappan:
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems.
HPCA 2008: 367-378 |
| 8 | | Hongzhong Zheng,
Jiang Lin,
Zhao Zhang,
Zhichun Zhu:
Memory Access Scheduling Schemes for Systems with Multi-Core Processors.
ICPP 2008: 406-413 |
| 7 | | Hongzhong Zheng,
Jiang Lin,
Zhao Zhang,
Eugene Gorbatov,
Howard David,
Zhichun Zhu:
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.
MICRO 2008: 210-221 |
| 6 | | Jiang Lin,
Hongzhong Zheng,
Zhichun Zhu,
Eugene Gorbatov,
Howard David,
Zhao Zhang:
Software thermal management of dram memory for multicore systems.
SIGMETRICS 2008: 337-348 |
| 2007 |
|---|
| 5 | | Yaqiang Ding,
Jiang Lin,
Yi Wang,
Fuhuei Lin,
Yi Kang:
A Scheme for System Multiplexing and Program Component Identification.
ICME 2007: 583-586 |
| 4 | | Jiang Lin,
Hongzhong Zheng,
Zhichun Zhu,
Howard David,
Zhao Zhang:
Thermal modeling and management of DRAM memory systems.
ISCA 2007: 312-322 |
| 3 | | Jiang Lin,
Hongzhong Zheng,
Zhichun Zhu,
Zhao Zhang,
Howard David:
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.
ISPASS 2007: 94-104 |
| 2005 |
|---|
| 2 | | Wei Huang,
Jiang Lin,
Zhao Zhang,
J. Morris Chang:
Performance Characterization of Java Applications on SMT Processors.
ISPASS 2005: 102-111 |
| 1 | | Wei Huang,
Jiang Lin,
Zhao Zhang,
J. Morris Chang:
Towards Pairing Java Applications on SMT Processors.
MASCOTS 2005: 7-14 |
