Yan Lin

	2009
33		Jinyu Tian, Yan Lin: Research on the Electric Power Enterprise Performance Evaluation Based on Symbiosis Theory. WKDD 2009: 64-67
32		Jinyu Tian, Yan Lin: Short-Term Electricity Price Forecasting Based on Rough Sets and Improved SVM. WKDD 2009: 68-71
31		Ren Zhang, Yan Lin: DEG 5.0, a database of essential genes in both prokaryotes and eukaryotes. Nucleic Acids Research 37(Database-Issue): 455-458 (2009)
	2008
30		Lerong Cheng, Yan Lin, Lei He: Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168
29		Yu Hu, Yan Lin, Lei He, Tim Tuan: Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
28		Yan Lin, George C. Tseng, Soo Yeon Cheong, Lora J. H. Bean, Stephanie L. Sherman, Eleanor Feingold: Smarter clustering methods for SNP genotype calling. Bioinformatics 24(23): 2665-2671 (2008)
27		Yan Lin, Lei He, Mike Hutton: Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. VLSI Syst. 16(2): 124-133 (2008)
26		Ren Zhang, Yan Lin, Chun-Ting Zhang: Greglist: a database listing potential G-quadruplex regulated genes. Nucleic Acids Research 36(Database-Issue): 372-376 (2008)
	2007
25		Yan Lin, Lei He: Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE 2007: 636-641
24		Yan Lin, Lei He: Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA 2007: 80-88
23		Yan Lin, Liu Qing: A Logical Method of Formalization for Granular Computing. GrC 2007: 22-27
22		Yan Lin, Lei He: Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD 2007: 194-198
21		Fei Li, Yan Lin, Lei He: Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 752-764 (2007)
20		Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He: Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1211-1221 (2007)
	2006
19		Yu Hu, Yan Lin, Lei He, Tim Tuan: Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC 2006: 478-483
18		Mike Hutton, Yan Lin, Lei He: Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7
17		Yan Lin, Yu Hu, Lei He, Vijay Raghunat: An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173
16		Yan Lin, Lei He: Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2023-2034 (2006)
	2005
15		Qiang Li, Yan Lin, Kun Liu, Jiubin Ju: Constructing Correlations in Attack Connection Chains Using Active Perturbation. AAIM 2005: 252-260
14		Yan Lin, Fei Li, Lei He: Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC 2005: 645-650
13		Yan Lin, Lei He: Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC 2005: 720-725
12		Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He: Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920
11		Yan Lin, Fei Li, Lei He: Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA 2005: 199-207
10		Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He: FPGA device and architecture evaluation considering process variations. ICCAD 2005: 19-24
9		Yan Lin, Fei Li, Lei He: Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. VLSI Syst. 13(9): 1035-1047 (2005)
	2004
8		Fei Li, Yan Lin, Lei He: FPGA power reduction using configurable dual-Vdd. DAC 2004: 735-740
7		Fei Li, Yan Lin, Lei He, Jason Cong: Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50
6		Fei Li, Yan Lin, Lei He: Vdd programmability to reduce FPGA interconnect power. ICCAD 2004: 760-765
	2003
5		Xiangui Kang, Jiwu Huang, Yun Q. Shi, Yan Lin: A DWT-DFT composite watermarking scheme robust to both affine transform and JPEG compression. IEEE Trans. Circuits Syst. Video Techn. 13(8): 776-786 (2003)
	1999
4		Anna Scaglione, Yan Lin, Georgios B. Giannakis: Block redundant constant modulus algorithm for channel-irrespective blind identifiability. NSIP 1999: 694-698
3		Yan Lin, Marek J. Druzdzel: Relevance-Based Incremental Belief Updating in Bayesian Networks. IJPRAI 13(2): 285-295 (1999)
	1998
2		Yan Lin, Marek J. Druzdzel: Relevance-Based Sequential Evidence Processing in Bayesian Networks. FLAIRS Conference 1998: 446-450
	1997
1		Yan Lin, Marek J. Druzdzel: Computational Advantages of Relevance Reasoning in Bayesian Belief Networks. UAI 1997: 342-350

Coauthor Index

1	Lora J. H. Bean	[28]
2	Lerong Cheng	[10] [12] [20] [30]
3	Soo Yeon Cheong	[28]
4	Jason Cong	[7]
5	Marek J. Druzdzel	[1] [2] [3]
6	Eleanor Feingold	[28]
7	Georgios B. Giannakis	[4]
8	Lei He	[6] [7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [18] [19] [20] [21] [22] [24] [25] [27] [29] [30]
9	Yu Hu	[17] [19] [29]
10	Jiwu Huang	[5]
11	Michael Hutton (Michael D. Hutton, Mike Hutton)	[18] [27]
12	Jiubin Ju	[15]
13	Xiangui Kang	[5]
14	Fei Li	[6] [7] [8] [9] [11] [12] [14] [20] [21]
15	Qiang Li	[15]
16	Kun Liu	[15]
17	Liu Qing	[23]
18	Vijay Raghunat	[17]
19	Anna Scaglione	[4]
20	Stephanie L. Sherman	[28]
21	Yun Q. Shi (Yun-Qing Shi)	[5]
22	Jinyu Tian	[32] [33]
23	George C. Tseng	[28]
24	Tim Tuan	[19] [29]
25	Ho-Yan Wong	[10]
26	Phoebe Wong	[12] [20]
27	Chun-Ting Zhang	[26]
28	Ren Zhang	[26] [31]

Colors in the list of coauthors