Youn-Long Lin

	2009
65		Huang-Chih Kuo, Jian-Wen Chen, Youn-Long Lin: A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. ESTImedia 2009: 1-8
64		Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo, Youn-Long Lin: An effective dictionary-based display frame compressor. ESTImedia 2009: 28-34
	2008
63		Huang-Chih Kuo, Youn-Long Lin: An H.264/AVC full-mode intra-frame encoder for 1080HD video. ICME 2008: 1037-1040
62		Cheng-Long Wu, Chao-Yang Kao, Youn-Long Lin: A high performance three-engine architecture for H.264/AVC fractional motion estimation. ICME 2008: 133-136
61		Chao-Yang Kao, Youn-Long Lin: A high-performance and memory-efficient architecture for H.264/AVC motion estimation. ICME 2008: 141-144
60		Ping Chao, Youn-Long Lin: Reference frame access optimization for ultra high resolution H.264/AVC decoding. ICME 2008: 1441-1444
59		Ping Chao, Youn-Long Lin: A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ISCAS 2008: 256-259
	2007
58		Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC CoRR abs/0710.4667: (2007)
	2006
57		Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin: A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. APCCAS 2006: 562-565
56		Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin: A near optimal deblocking filter for H.264 advanced video coding. ASP-DAC 2006: 170-175
55		Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin: Introduction to H.264 advanced video coding. ASP-DAC 2006: 736-741
54		Chao-Yang Kao, Huang-Chih Kuo, Youn-Long Lin: High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. ICME 2006: 1241-1244
	2005
53		Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC. DATE 2005: 1116-1117
52		Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin: A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ISCAS (5) 2005: 4525-4528
51		Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin: An AMBA-compliant deblocking filter IP for H.264/AVC. ISCAS (5) 2005: 4529-4532
50		Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin: A platform based SOC design methodology and its application in image compression. IJES 1(1/2): 23-32 (2005)
	2004
49		Tien-Wei Hsieh, Youn-Long Lin: A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. ESTImedia 2004: 87-90
	2002
48		Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-
47		Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-
46		Yih-Chih Chou, Youn-Long Lin: Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 15-22 (2002)
	2001
45		Yih-Chih Chou, Youn-Long Lin: A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191
44		Yih-Chih Chou, Youn-Long Lin: A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29
43		Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin: Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. ISSS 2001: 233-238
	2000
42		Michael C.-J. Lin, Youn-Long Lin: A VLSI implementation of the blowfish encryption/decryption algorithm. ASP-DAC 2000: 1-2
41		Tzu-Chieh Tien, Youn-Long Lin: Performance-optimal clustering with retiming for sequential circuits. ASP-DAC 2000: 409-414
40		Hong-Kai Chang, Youn-Long Lin: Array allocation taking into account SDRAM characteristics. ASP-DAC 2000: 497-502
	1999
39		Yun-Yin Lian, Youn-Long Lin: Layout-based Logic Decomposition for Timing Optimization. ASP-DAC 1999: 229-232
38		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267
37		Wei-Kai Cheng, Youn-Long Lin: Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4(3): 231-256 (1999)
36		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999)
	1998
35		Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin: Integrating logic retiming and register placement. ICCAD 1998: 136-139
34		Yih-Chih Chou, Youn-Long Lin: A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429
33		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17
32		Wei-Kai Cheng, Youn-Long Lin: Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS 1998: 15-22
	1997
31		Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin: Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174
30		Youn-Long Lin: Recent developments in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 2(1): 2-21 (1997)
29		Hsiao-Pin Su, Youn-Long Lin: A phase assignment method for virtual-wire-based hardware emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 776-783 (1997)
	1996
28		Tsung-Yi Wu, Youn-Long Lin: Register minimization beyond sharing among variables. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1583-1587 (1996)
	1995
27		Wei-Kai Cheng, Youn-Long Lin: A Transformation-Based Approach for Storage Optimization. DAC 1995: 158-163
26		Tsung-Yi Wu, Youn-Long Lin: Register Minimization beyond Sharing among Variables. DAC 1995: 164-169
25		Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin: TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 371-374 (1995)
24		Yu-Wen Tsay, Youn-Long Lin: A row-based cell placement method that utilizes circuit structural properties. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 393-397 (1995)
23		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
	1994
22		Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281
21		Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
20		Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994)
19		Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski: A transformation-based method for loop folding. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994)
	1993
18		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
17		Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993)
16		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: PLS: a scheduler for pipeline synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1279-1286 (1993)
	1992
15		Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin: An effective methodology for functional pipelining. ICCAD 1992: 230-233
14		Yirng-An Chen, Youn-Long Lin, Long-Wen Chang: A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers 41(1): 103-108 (1992)
	1991
13		Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin: Channel Density Reduction by Routing Over The Cells. DAC 1991: 120-125
12		Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486
11		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769
10		Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao: Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991)
9		Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin: Channel density reduction by routing over the cells. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1067-1071 (1991)
8		Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: a CMOS cell compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991)
	1990
7		Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: A Cell Layout Generator. DAC 1990: 474-479
6		Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu: Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504
5		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70
4		Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: Hybrid routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990)
3		Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu: A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990)
	1989
2		Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: SILK: a simulated evolution router. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989)
	1988
1		Youn-Long Lin, Daniel D. Gajski: LES: a layout expert system. IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 868-876 (1988)

Coauthor Index

1	Cheng-Ru Chang	[51] [52] [56]
2	Hong-Kai Chang	[40]
3	Long-Wen Chang	[14]
4	Ping Chao	[59] [60]
5	Ting-Hai Chao	[10]
6	Chau-Shen Chen	[18] [23]
7	Chien-Liang Chen	[53] [58]
8	Ching-Dong Chen	[25]
9	Jian-Wen Chen	[52] [55] [64] [65]
10	Yen-Shen Chen	[6]
11	Yirng-An Chen	[14]
12	Kuo-Liang Cheng	[47] [48]
13	Wei-Kai Cheng	[27] [32] [37]
14	Yih-Chih Chou	[34] [35] [44] [45] [46]
15	Chih-Bin Fan	[50]
16	Wen-Jong Fang	[31]
17	Daniel Gajski (Daniel D. Gajski)	[1] [15] [19]
18	Chia-Wen Hou	[57]
19	Hang-Ching Hsieh	[10]
20	Tien-Wei Hsieh	[49]
21	Yung-Chin Hsieh	[3]
22	Yung-Ching Hsieh	[7] [8] [12] [17]
23	Huan-Shan Hsu	[47]
24	Yu-Chin Hsu	[2] [3] [4] [5] [6] [7] [8] [10] [11] [12] [16] [17]
25	Chih-Tsun Huang	[47] [48]
26	Chu-Yi Huang	[6]
27	Hao-Tin Huang	[57]
28	Jing-Reng Huang	[47] [48]
29	Cheng-Tsung Hwang	[5] [11] [16]
30	Chi-Yi Hwang	[3] [7] [8] [9] [12] [13] [17]
31	TingTing Hwang	[18] [20] [21] [23]
32	Kai-Yuan Jan	[50]
33	Yi-Min Jiang	[20]
34	Chao-Yang Kao	[54] [55] [61] [62]
35	Yu-Chien Kao	[57]
36	An-Chao Kuo	[50]
37	Huang-Chih Kuo	[54] [57] [63] [64] [65]
38	Tsing-Fa Lee	[15] [19] [20]
39	Yuh-Sheng Lee	[25]
40	Yi-Hsien Li	[57]
41	Yun-Yin Lian	[39]
42	Chien-Yu Lin	[43]
43	Jiing-Yuan Lin	[53] [58]
44	Michael C.-J. Lin	[42]
45	Min-Siang Lin	[9] [13]
46	Yen-Fu Lin	[48]
47	Yin-Tzu Lin	[57]
48	Houng-Wern Perng	[9]
49	Hourng-Wern Perng	[13]
50	Shen-Yu Shih	[56]
51	Sheng-Yu Shih	[51]
52	Hsiao-Pin Su	[29] [33] [35] [36] [38]
53	Tzu-Chieh Tien	[22] [35] [41]
54	Fur-Shing Tsai	[2] [4]
55	Yu-Wen Tsay	[18] [23] [24] [31] [35]
56	Chih-Wea Wang	[47] [48]
57	Kuo-Hua Wang	[21]
58	Wen-Sing Wang	[21]
59	Hung-Pin Wen	[43]
60	Allen C.-H. Wu	[15] [18] [19] [21] [22] [23] [25] [31] [33] [36] [38]
61	Cheng-Long Wu	[62]
62	Cheng-Wen Wu	[47] [48]
63	Tsung-Yi Wu	[22] [26] [28]
64	Hui-Ting Yang	[64]
65	Wen-Chi Yen	[50]

Colors in the list of coauthors