| 2009 | ||
|---|---|---|
| 48 | Yi-Chih Chao, Shih-Tse Wei, Bin-Da Liu, Jar-Ferr Yang: Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder. IEEE Trans. Circuits Syst. Video Techn. 19(1): 53-62 (2009) | |
| 2008 | ||
| 47 | Yi-Chih Chao, Kuan-Hung Lin, Bin-Da Liu, Jar-Ferr Yang: An approximate square criterion for H.264/AVC intra mode decision. ICME 2008: 333-336 | |
| 46 | Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu, Bin-Da Liu: System level design of a spatio-temporal video resampling architecture. ISCAS 2008: 2797-2800 | |
| 45 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu: A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. IEEE Trans. VLSI Syst. 16(6): 677-682 (2008) | |
| 44 | Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang: A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder. IEEE Transactions on Multimedia 10(1): 31-42 (2008) | |
| 43 | Hsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu: Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. IEICE Transactions 91-A(2): 461-468 (2008) | |
| 42 | Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu, Soon-Jyh Chang: A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. IEICE Transactions 91-C(5): 809-812 (2008) | |
| 41 | Hsin-Hung Ou, Bin-Da Liu, Soon-Jyh Chang: A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. IEICE Transactions 91-C(9): 1480-1487 (2008) | |
| 2007 | ||
| 40 | Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, Bin-Da Liu: A Novel Design for Computation of All Transforms in H.264/AVC Decoders. ICME 2007: 1914-1917 | |
| 39 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu: Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. ISCAS 2007: 3135-3138 | |
| 38 | Li-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu: A Real Time and Low Cost Hardware Architecture for Video Abstraction System. ISCAS 2007: 773-776 | |
| 37 | Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang: Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electronic Testing 23(6): 549-558 (2007) | |
| 2006 | ||
| 36 | Yi-Chih Chao, Ji-Kun Lin, Jar-Ferr Yang, Bin-Da Liu: A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter. APCCAS 2006: 1260-1263 | |
| 35 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu: A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. APCCAS 2006: 1293-1296 | |
| 34 | Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang: An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. APCCAS 2006: 255-258 | |
| 33 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu: Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. APCCAS 2006: 259-262 | |
| 32 | Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu: A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. APCCAS 2006: 426-429 | |
| 31 | Heng-Yao Lin, Jwu-Jin Yang, Bin-Da Liu, Jar-Ferr Yang: Efficient deblocking filter architecture for H.264 video coders. ISCAS 2006 | |
| 30 | Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang: Low power design of H.264 CAVLC decoder. ISCAS 2006 | |
| 29 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu: A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. ISLPED 2006: 135-138 | |
| 2005 | ||
| 28 | Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang: Combined 2-D transform and quantization architectures for H.264 video coders. ISCAS (2) 2005: 1802-1805 | |
| 27 | Hsin-Hung Ou, Bin-Da Liu: A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. ISCAS (3) 2005: 1972-1975 | |
| 26 | Chung-Bin Wu, C.-Y. Yao, Bin-Da Liu, Jar-Ferr Yang: DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. IEEE Trans. Circuits Syst. Video Techn. 15(5): 694-703 (2005) | |
| 2004 | ||
| 25 | Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang: A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. Asian Test Symposium 2004: 52-57 | |
| 24 | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang: Condensed recursive structures for computing multi-dimensional DCT with arbitrary length. ISCAS (3) 2004: 405-408 | |
| 23 | Zhan-Yuan Cheng, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang: Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering. ISCAS (3) 2004: 557-560 | |
| 22 | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu: A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. ISLPED 2004: 252-256 | |
| 21 | Wen-Bin Lin, Bin-Da Liu: Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters. IEICE Transactions 87-A(1): 231-242 (2004) | |
| 2003 | ||
| 20 | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang: Direct recursive structures for computing radix-r two-dimensional DCT. ISCAS (4) 2003: 269-272 | |
| 19 | Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu: Low-power and low-voltage fully parallel content-addressable memory. ISCAS (5) 2003: 373-376 | |
| 18 | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang: Adaptive postprocessors with DCT-based block classifications. IEEE Trans. Circuits Syst. Video Techn. 13(5): 365-375 (2003) | |
| 2002 | ||
| 17 | Wen-Bin Lin, Bin-Da Liu: The high-resolution multi-tone signal generators. APCCAS (1) 2002: 245-250 | |
| 16 | Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu: A scalable sorting architecture based on maskable WTA/MAX circuit. ISCAS (4) 2002: 209-212 | |
| 15 | Chi-Sheng Lin, Bin-Da Liu: Design of a pipelined and expandable sorting architecture with simple control scheme. ISCAS (4) 2002: 217-220 | |
| 2001 | ||
| 14 | Chien-Cheng Yu, Wei-Ping Wang, Bin-Da Liu: A new level converter for low-power applications. ISCAS (1) 2001: 113-116 | |
| 13 | Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu: A hardware design approach for merge-sorting network. ISCAS (4) 2001: 534-537 | |
| 12 | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang: Adaptive postprocessors with DCT-based block classifications. ISCAS (5) 2001: 271-274 | |
| 11 | Bin-Da Liu, Chuen-Yau Chen, Ju-Ying Tsao: Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms. IEEE Transactions on Systems, Man, and Cybernetics, Part B 31(1): 32-53 (2001) | |
| 1998 | ||
| 10 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A graph representation for programmable logic arrays to facilitate testing and logic design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1030-1043 (1998) | |
| 1997 | ||
| 9 | Bin-Da Liu, Chun-Yueh Huang: Design and implementation of the tree-based fuzzy logic controller. IEEE Transactions on Systems, Man, and Cybernetics, Part B 27(3): 475-487 (1997) | |
| 1995 | ||
| 8 | Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee: An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). ISCAS 1995: 393-396 | |
| 7 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang: Performance-directed compaction for VLSI symbolic layouts. Computer-Aided Design 27(1): 65-74 (1995) | |
| 6 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A practical current sensing technique for IDDQ testing. IEEE Trans. VLSI Syst. 3(2): 302-310 (1995) | |
| 1994 | ||
| 5 | Bin-Da Liu, Chun-Yueh Huang: Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits. ISCAS 1994: 537-540 | |
| 1993 | ||
| 4 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang: A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. ICCAD 1993: 703-708 | |
| 3 | Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu: Functional Text Pattern Generation for Asynchronous Circuits. ISCAS 1993: 1519-1522 | |
| 2 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang: Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. ISCAS 1993: 1849-1852 | |
| 1992 | ||
| 1 | Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang: Overall consideration of scan design and test generation. ICCAD 1992: 9-12 | |