Chia-Hsien Liu

	2005
2		Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen: A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55
1		Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen: Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) 2005: 3503-3506

Coauthor Index

1	Chie-Min Chao	[1] [2]
2	Shin-Kai Chen	[1] [2]
3	Pi-Chen Hsiao	[1] [2]
4	Chao-Wei Huang	[1]
5	Chein-Wei Jen	[1] [2]
6	Li-Chun Lin	[1] [2]
7	Tay-Jyi Lin	[1] [2]
8	Chih-Wei Liu	[1] [2]