 | 2009 |
|---|
| 9 |       | Po-Yang Hsu,
Shu-Ting Lee,
Fu-Wei Chen,
Yi-Yu Liu:
Buffer design and optimization for lut-based structured ASIC design styles.
ACM Great Lakes Symposium on VLSI 2009: 377-380 |
| 8 | | Fu-Wei Chen,
Yi-Yu Liu:
Performance-driven dual-rail insertion for chip-level pre-fabricated design.
DATE 2009: 308-311 |
| 2008 |
|---|
| 7 | | Fu-Wei Chen,
Yi-Yu Liu:
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.
DATE 2008: 796-799 |
| 2007 |
|---|
| 6 | | Yi-Yu Liu,
TingTing Hwang:
Crosstalk-Aware Domino-Logic Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1155-1161 (2007) |
| 2006 |
|---|
| 5 | | Yi-Yu Liu,
TingTing Hwang:
Crosstalk-aware domino logic synthesis.
DATE 2006: 1312-1317 |
| 4 | | Yi-Yu Liu,
Kuo-Hua Wang,
TingTing Hwang:
Crosstalk minimization in logic synthesis for PLAs.
ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006) |
| 2004 |
|---|
| 3 | | Yi-Yu Liu,
Kuo-Hua Wang,
TingTing Hwang:
Crosstalk Minimization in Logic Synthesis for PLA.
DATE 2004: 790-795 |
| 2001 |
|---|
| 2 | | LiYi Lin,
Yi-Yu Liu,
TingTing Hwang:
A construction of minimal delay Steiner tree using two-pole delay model.
ASP-DAC 2001: 126-132 |
| 1 | | Yi-Yu Liu,
Kuo-Hua Wang,
TingTing Hwang,
C. L. Liu:
Binary decision diagram with minimum expected path length.
DATE 2001: 708-712 |
