José María Llabería

José M. Llabería

	2009
42		Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José María Llabería: A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161
41		Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería: On reducing misspeculations in a pipelined scheduler. IPDPS 2009: 1-12
	2007
40		Enric Morancho, José María Llabería, Àngel Olivé: On reducing energy-consumption by late-inserting instructions into the issue queue. ISLPED 2007: 371-374
39		Enric Morancho, José María Llabería, Àngel Olivé: A comparison of two policies for issuing instructions speculatively. Journal of Systems Architecture 53(4): 170-183 (2007)
	2006
38		A. de Dios, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería: Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484
37		Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería: An Enhancement for a Scheduling Logic Pipelined over two Cycles . ICCD 2006
	2005
36		Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480
35		María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. TACO 2(3): 247-279 (2005)
	2004
34		Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524
33		Enric Morancho, José María Llabería, Àngel Olivé: A Mechanism for Verifying Data Speculation. Euro-Par 2004: 525-534
	2003
32		Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596
31		María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202
30		María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas: Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-
29		Marta Jiménez, José M. Llabería, Agustin Fernández: A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distrib. Syst. 14(10): 1006-1020 (2003)
	2002
28		Marta Jiménez, José M. Llabería, Agustin Fernández: Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. 24(4): 409-453 (2002)
	2001
27		Enric Morancho, José María Llabería, Àngel Olivé: Recovery Mechanism for Latency Misprediction. IEEE PACT 2001: 118-
	2000
26		Enric Morancho, José M. Llabería, Àngel Olivé: Two-Level Address Storage and Address Prediction (Research Note). Euro-Par 2000: 960-964
25		Marta Jiménez, José M. Llabería, Agustin Fernández: On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA 2000: 183-194
	1999
24		Enric Morancho, José M. Llabería, Àngel Olivé: Looking at History to Filter Allocations in Prediction Tables. IEEE PACT 1999: 314-319
23		A. M. del Corral, José M. Llabería: Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. IEEE Trans. Computers 48(4): 449-456 (1999)
	1998
22		Marta Jiménez, José M. Llabería, Agustin Fernández: Performance Evaluation of Tiling for the Register Level. HPCA 1998: 254-265
21		Enric Morancho, José M. Llabería, Àngel Olivé: Split Last-Address Predictor. IEEE PACT 1998: 230-
20		Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho: A General Algorithm for Tiling the Register Level. International Conference on Supercomputing 1998: 133-140
19		A. M. del Corral, José M. Llabería: New Access Order to Reduce Inter-Vector-Conflicts. VECPAR 1998: 425-438
	1996
18		A. M. del Corral, José M. Llabería: Increasing the Effective Memory Bandwidth in Multivector Processors. EUROMICRO 1996: 38-45
17		Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho: A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I 1996: 402-405
16		A. M. del Corral, José M. Llabería: Reducing Inter-Vector-Conflicts in Complex Memory Systems. International Conference on Supercomputing 1996: 382-389
	1995
15		A. M. del Corral, José M. Llabería: Access order to avoid inter-vector-conflicts in complex memory systems. IPPS 1995: 404-410
14		Agustin Fernández, José M. Llabería, Miguel Valero-García: Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distrib. Syst. 6(8): 832-840 (1995)
	1993
13		Antonio González, José M. Llabería: Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers 42(3): 363-371 (1993)
	1992
12		Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro: Increasing the Number of Strides for Conflict-Free Vector Access. ISCA 1992: 372-381
11		Jordi Cortadella, José M. Llabería: Evaluation of A + B = K Conditions Without Carry Propagation. IEEE Trans. Computers 41(11): 1484-1488 (1992)
10		Miguel Valero-García, Juan J. Navarro, José María Llabería, Mateo Valero, Tomás Lang: A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. VLSI Signal Processing 4(1): 7-25 (1992)
	1991
9		Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero: On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC 1991: 173-182
8		Agustin Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García: Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC 1991: 90-99
7		Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería: Balanced Loop Partitioning Using GTS. LCPC 1991: 298-312
6		Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé: Conflict-Free Strides for Vectors in Matched Memories. Parallel Processing Letters 1: 95-102 (1991)
	1989
5		Antonio González, José M. Llabería: Instruction fetch unit for parallel execution of branch instructions. ICS 1989: 417-426
4		Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero: Systematic Hardware Adaptation of Systolic Algorithms. ISCA 1989: 96-104
	1986
3		Juan J. Navarro, José M. Llabería, Mateo Valero: Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP 1986: 676-683
2		Juan J. Navarro, José M. Llabería, Mateo Valero: Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA 1986: 271-278
	1985
1		José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta: Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA 1985: 414-421

Coauthor Index

1	Eduard Ayguadé	[6] [7] [9] [12]
2	A. M. del Corral	[15] [16] [18] [19] [23]
3	Jordi Cortadella	[11]
4	A. de Dios	[38]
5	Agustin Fernández	[8] [14] [17] [20] [22] [25] [28] [29]
6	Benjamín Sahelices Fernández	[38] [42]
7	María Jesús Garzarán	[30] [31] [35]
8	Antonio González	[5] [13]
9	Pablo Ibáñez	[32] [34] [36] [38] [42]
10	Marta Jiménez	[17] [20] [22] [25] [28] [29]
11	Jesús Labarta	[1] [7] [9]
12	Tomás Lang	[6] [10] [12]
13	Enrique Herrada Lillo	[1]
14	Enric Morancho	[17] [20] [21] [24] [26] [27] [33] [37] [39] [40] [41]
15	Juan J. Navarro	[2] [3] [4] [6] [8] [10] [12]
16	Àngel Olivé	[21] [24] [26] [27] [33] [37] [39] [40] [41]
17	Montse Peiron	[6] [12]
18	Milos Prvulovic	[30] [31] [35]
19	Lawrence Rauchwerger	[30] [31] [35]
20	Ruben Gran Tejero	[37] [41]
21	Josep Torrellas	[30] [31] [35]
22	Enrique F. Torres	[32] [34] [36]
23	Jordi Torres	[7] [9]
24	Mateo Valero	[1] [2] [3] [4] [6] [7] [9] [10] [12]
25	Miguel Valero-García	[4] [8] [10] [14]
26	Víctor Viñals (Víctor Viñals Yúfera)	[30] [31] [32] [34] [35] [36] [38] [42]

Colors in the list of coauthors