Xiang Lu

	2007
16		Xiang Lu, Shuqian Luo: The Application of Watersnakes Algorithm in Segmentation of the Hippocampus from Brain MR Image. MIMI 2007: 277-286
15		Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger: Modeling Power Supply Noise in Delay Testing. IEEE Design & Test of Computers 24(3): 226-234 (2007)
	2006
14		Wei Tang, Qing-Guo Wang, Xiang Lu, Zhiping Zhang: Why Ti=4Td for PID Controller Tuning. ICARCV 2006: 1-2
13		Xiang Lu, Jiajia Chen, Sailing He: An Algorithm for Constructing All Families of Codes of Arbitrary Requirement in an OCDMA System CoRR abs/cs/0601088: (2006)
	2005
12		Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker: Static Compaction of Delay Tests Considering Power Supply Noise. VTS 2005: 235-240
11		Yi-Jen Chiang, Tobias Lenz, Xiang Lu, Günter Rote: Simple and optimal output-sensitive construction of contour trees using monotone paths. Comput. Geom. 30(2): 165-195 (2005)
10		Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: Longest-path selection for delay test under process variation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1924-1929 (2005)
	2004
9		Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: Longest path selection for delay test under process variation. ASP-DAC 2004: 98-103
8		Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED 2004: 276-280
7		Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi: A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV 2004: 97-102
6		Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi: A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS 2004: 37-42
	2003
5		Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi: CodSim -- A Combined Delay Fault Simulator. DFT 2003: 79-
4		Zhuo Li, Xiang Lu, Weiping Shi: Process variation dimension reduction based on SVD. ISCAS (4) 2003: 672-675
3		Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker: A Circuit Level Fault Model for Resistive Opens and Bridges. VTS 2003: 379-384
2		Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker: A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003)
1		Yi-Jen Chiang, Xiang Lu: Progressive Simplification of Tetrahedral Meshes Preserving All Isosurface Topologies. Comput. Graph. Forum 22(3): 493-504 (2003)

Coauthor Index

1	Jiajia Chen	[13]
2	Yi-Jen Chiang	[1] [11]
3	Stefan Eichenberger	[15]
4	Steve Fancler	[12]
5	Guido Gronthoud	[15]
6	Sailing He	[13]
7	Bram Kruseman	[15]
8	Tobias Lenz	[11]
9	Zhuo Li	[2] [3] [4] [5] [6] [7] [8] [9] [10]
10	Shuqian Luo	[16]
11	Ananta K. Majhi	[15]
12	Wangqi Qiu	[2] [3] [5] [6] [7] [8] [9] [10] [12]
13	Günter Rote	[11]
14	Weiping Shi	[2] [3] [4] [5] [6] [7] [8] [9] [10] [12]
15	Wei Tang	[14]
16	Luis Elvira Villagra	[15]
17	D. M. H. Walker (Duncan M. Hank Walker)	[2] [3] [5] [6] [7] [8] [9] [10] [12] [15]
18	Qing-Guo Wang	[14]
19	Jing Wang	[6] [12] [15]
20	Paul J. A. M. van de Wiel	[15]
21	Ziding Yue	[12]
22	Zhiping Zhang	[14]

Colors in the list of coauthors