Roman L. Lysecky

	2009
30		Karthik Shankar, Roman L. Lysecky: Non-intrusive dynamic application profiling for multitasked applications. DAC 2009: 130-135
29		Roman L. Lysecky, Frank Vahid: Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embedded Comput. Syst. 8(3): (2009)
	2008
28		Ajay Nair, Roman L. Lysecky: Non-intrusive dynamic application profiler for detailed loop execution characterization. CASES 2008: 23-30
27		Lance Saldanha, Roman L. Lysecky: Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. CODES+ISSS 2008: 49-54
26		Mark Hammerquist, Roman L. Lysecky: Design space exploration for application specific FPGAS in system-on-a-chip designs. SoCC 2008: 279-282
25		Frank Vahid, Greg Stitt, Roman L. Lysecky: Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer 41(7): 40-46 (2008)
24		Roman L. Lysecky: Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning. International Journal of Parallel Programming 36(5): 478-492 (2008)
	2007
23		Roman L. Lysecky: Low-power warp processor for power efficient high-performance embedded systems. DATE 2007: 141-146
22		Roman L. Lysecky, Frank Vahid: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning CoRR abs/0710.4705: (2007)
	2006
21		David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen: Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268
20		David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky: Conjoining soft-core FPGA processors. ICCAD 2006: 694-701
19		Roman L. Lysecky, Greg Stitt, Frank Vahid: Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006)
	2005
18		Roman L. Lysecky, Frank Vahid: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. DATE 2005: 18-23
17		Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62
16		Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers: Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA 2005: 271
	2004
15		Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959
14		Chuanjun Zhang, Frank Vahid, Roman L. Lysecky: A Self-Tuning Cache Architecture for Embedded Systems. DATE 2004: 142-147
13		Roman L. Lysecky, Frank Vahid: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. DATE 2004: 480-485
12		Chuanjun Zhang, Frank Vahid, Roman L. Lysecky: A self-tuning cache architecture for embedded systems. ACM Trans. Embedded Comput. Syst. 3(2): 407-425 (2004)
11		Roman L. Lysecky, Susan Cotterell, Frank Vahid: A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. VLSI Syst. 12(1): 120-122 (2004)
	2003
10		Roman L. Lysecky, Frank Vahid: A codesigned on-chip logic minimizer. CODES+ISSS 2003: 109-113
9		Greg Stitt, Roman L. Lysecky, Frank Vahid: Dynamic hardware/software partitioning: a first approach. DAC 2003: 250-255
8		Roman L. Lysecky, Frank Vahid: On-chip logic minimization. DAC 2003: 334-337
7		Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt: Highly configurable platforms for embedded computing systems. Microelectronics Journal 34(11): 1025-1029 (2003)
	2002
6		Roman L. Lysecky, Susan Cotterell, Frank Vahid: A fast on-chip profiler memory. DAC 2002: 28-33
5		Roman L. Lysecky, Frank Vahid: Prefetching for improved bus wrapper performance in cores. ACM Trans. Design Autom. Electr. Syst. 7(1): 58-90 (2002)
	2000
4		Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky: A first-step towards an architecture tuning methodology for low power. CASES 2000: 187-192
3		Roman L. Lysecky, Frank Vahid, Tony Givargis: Techniques for Reducing Read Latency of Core Bus Wrappers. DATE 2000: 84-91
2		Roman L. Lysecky, Frank Vahid, Tony Givargis: Experiments with the Peripheral Virtual Component Interface. ISSS 2000: 221-224
	1999
1		Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis: Pre-Fetching for Improved Core Interfacing. ISSS 1999: 51-55

Coauthor Index

1	Susan Cotterell	[6] [11]
2	Tony Givargis	[1] [2] [3] [4]
3	Mark Hammerquist	[26]
4	Rakesh Kumar	[20] [21]
5	Kris Miller	[16]
6	Ajay Nair	[28]
7	Rilesh Patel	[1]
8	Lance Saldanha	[27]
9	Karthik Shankar	[30]
10	David Sheldon	[20] [21]
11	Greg Stitt	[4] [7] [9] [19] [25]
12	Sheldon X.-D. Tan (Xiang-Dong Tan)	[15] [17]
13	Dean M. Tullsen	[20] [21]
14	Frank Vahid	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [25] [29]
15	Kees A. Vissers	[16]
16	Chuanjun Zhang	[7] [12] [14]

Colors in the list of coauthors