Yuchun Ma

	2009
35		Xin Li, Yuchun Ma, Xianlong Hong: A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC 2009: 347-352
34		Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong: Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286
33		Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong: Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745
	2008
32		Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212
31		Jiemin Liu, Yuchun Ma, Yuan Gao: MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer. FSKD (4) 2008: 86-90
30		Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong: IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876
29		Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong: Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. JETC 4(4): (2008)
	2007
28		Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569
27		Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong: Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196
26		Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925
25		Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou: 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597
24		Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong: Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266
23		Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047
22		Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong: Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124
21		Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma: An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32
	2006
20		Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795
19		Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang: An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389
18		Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006)
	2005
17		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866
16		Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225
15		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219
14		Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633
13		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu: Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005)
	2004
12		Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620
11		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623
10		Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004)
9		Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu: Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004)
	2003
8		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811
7		Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711
6		Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu: Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496
5		Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142
	2002
4		Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. VLSI Design 2002: 387-392
	2001
3		Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514
2		Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775
1		Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with abutment constraints based on corner block list. Integration 31(1): 65-77 (2001)

Coauthor Index

1	Jinian Bian	[28]
2	Yici Cai	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12]
3	Song Chen	[5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17]
4	Chung-Kuan Cheng	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
5	Jason Cong	[19] [24] [26] [29] [32]
6	Robert P. Dick	[25]
7	Sheqin Dong	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21] [22] [23] [26] [27] [28] [32] [33]
8	Yuan Gao	[31]
9	Jun Gu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [18]
10	Ou He	[28]
11	Xiangqing He	[30] [34]
12	Xu He	[33]
13	Xianlong Hong	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21] [22] [23] [25] [26] [27] [28] [30] [32] [33] [34] [35]
14	Ashok Jagannathan	[19]
15	Eren Kursun	[24] [29]
16	Xin Li	[32] [35]
17	Zhuoyuan Li	[25] [26]
18	Jiayi Liu	[27]
19	Jiemin Liu	[31]
20	Yongxiang Liu	[24] [29]
21	Di Long	[27]
22	Xiang Qiu	[30] [34]
23	Glenn Reinman	[19] [24] [26] [29]
24	Li Shang	[25]
25	Jie Wei	[19]
26	Yaoguang Wei	[21]
27	Liu Yang	[20] [22]
28	Lingyi Zhang	[23]
29	Yan Zhang	[19]
30	Hai Zhou	[25]
31	Pingqiang Zhou	[25]
32	Qiang Zhou	[25] [26]

Colors in the list of coauthors