 | 2008 |
|---|
| 8 |       | Koushik Maharatna,
Karim El-Shabrawy,
Bashir M. Al-Hashimi:
Reduced Z-datapath Cordic Rotator.
ISCAS 2008: 3374-3377 |
| 2007 |
|---|
| 7 | | Alfonso Troya,
Koushik Maharatna,
Milos Krstic,
Eckhard Grass,
Ulrich Jagdhold,
Rolf Kraemer:
Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture.
IEEE Transactions on Wireless Communications 6(4): 1374-1385 (2007) |
| 2006 |
|---|
| 6 | | Koushik Maharatna,
Alfonso Troya,
Milos Krstic,
Eckhard Grass:
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder.
VLSI Design 2006: 613-618 |
| 2005 |
|---|
| 5 | | Koushik Maharatna,
Swapna Banerjee,
Eckhard Grass,
Milos Krstic,
Alfonso Troya:
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.
IEEE Trans. Circuits Syst. Video Techn. 15(11): 1463-1474 (2005) |
| 2004 |
|---|
| 4 |  | Koushik Maharatna,
Alfonso Troya,
Milos Krstic,
Eckhard Grass,
Ulrich Jagdhold:
A CORDIC like processor for computation of arctangent and absolute magnitude of a vector.
ISCAS (2) 2004: 713-716 |
| 2002 |
|---|
| 3 | | Eckhard Grass,
Bodhisatya Sarker,
Koushik Maharatna:
A Dual-Mode Synchronous/Asynchronous CORDIC Processor.
ASYNC 2002: 76-83 |
| 2001 |
|---|
| 2 | | Koushik Maharatna,
Swapna Banerjee:
A VLSI array architecture for Hough transform.
Pattern Recognition 34(7): 1503-1512 (2001) |
| 1 | | Koushik Maharatna,
A. S. Dhar,
Swapna Banerjee:
A VLSI array architecture for realization of DFT, DHT, DCT and DST.
Signal Processing 81(9): 1813-1822 (2001) |
