Naresh Maheshwari

	1999
7		Naresh Maheshwari, Sachin S. Sapatnekar: Optimizing large multiphase level-clocked circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1249-1264 (1999)
6		Naresh Maheshwari, Sachin S. Sapatnekar: Retiming control logic. Integration 28(1): 33-53 (1999)
	1998
5		Naresh Maheshwari, Sachin S. Sapatnekar: Efficient Minarea Retiming of Large Level-Clocked Circuits. DATE 1998: 840-
4		Naresh Maheshwari, Sachin S. Sapatnekar: Efficient retiming of large circuits. IEEE Trans. VLSI Syst. 6(1): 74-83 (1998)
	1997
3		Naresh Maheshwari, Sachin S. Sapatnekar: An Improved Algorithm for Minimum-Area Retiming. DAC 1997: 2-7
2		Naresh Maheshwari, Sachin S. Sapatnekar: Minimum area retiming with equivalent initial states. ICCAD 1997: 216-219
	1996
1		Naresh Maheshwari, Sachin S. Sapatnekar: A Practical Algorithm for Retiming Level-Clocked Circuits. ICCD 1996: 440-

Coauthor Index

1

Sachin S. Sapatnekar

[1] [2] [3] [4] [5] [6] [7]