 | 2009 |
|---|
| 104 |       | Yongjun Park,
Hyunchul Park,
Scott A. Mahlke:
CGRA express: accelerating execution using dynamic operation fusion.
CASES 2009: 271-280 |
| 103 | | Kevin Fan,
Manjunath Kudlur,
Ganesh S. Dasika,
Scott A. Mahlke:
Bridging the computation gap between programmable processors and hardwired accelerators.
HPCA 2009: 313-322 |
| 102 | | Mark Woh,
Sangwon Seo,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
AnySP: anytime anywhere anyway signal processing.
ISCA 2009: 128-139 |
| 101 | | Amin Ansari,
Shuguang Feng,
Shantanu Gupta,
Scott A. Mahlke:
Enabling ultra low voltage system operation by tolerating on-chip cache failures.
ISLPED 2009: 307-310 |
| 100 | | Taewook Oh,
Bernhard Egger,
Hyunchul Park,
Scott A. Mahlke:
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.
LCTES 2009: 21-30 |
| 99 | | Amir Hormati,
Yoonseo Choi,
Manjunath Kudlur,
Rodric M. Rabbah,
Trevor N. Mudge,
Scott A. Mahlke:
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures.
PACT 2009: 214-223 |
| 98 | | Mojtaba Mehrara,
Jeff Hao,
Po-Chun Hsu,
Scott A. Mahlke:
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory.
PLDI 2009: 166-176 |
| 97 | | Yin Wang,
Stéphane Lafortune,
Terence Kelly,
Manjunath Kudlur,
Scott A. Mahlke:
The theory of deadlock avoidance via discrete control.
POPL 2009: 252-263 |
| 96 | | Hyunchul Park,
Yongjun Park,
Scott A. Mahlke:
A dataflow-centric approach to design low power control paths in CGRAs.
SASP 2009: 15-20 |
| 95 | | Ganesh S. Dasika,
Kevin Fan,
Scott A. Mahlke:
Power-efficient medical image processing using PUMA.
SASP 2009: 29-34 |
| 94 | | Amin Ansari,
Dan Zhang,
Scott A. Mahlke:
Parade: A versatile parallel architecture for accelerating pulse train clustering.
SASP 2009: 88-93 |
| 2008 |
|---|
| 93 | | Shantanu Gupta,
Shuguang Feng,
Amin Ansari,
Jason A. Blome,
Scott A. Mahlke:
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems.
CASES 2008: 1-10 |
| 92 | | Amir Hormati,
Manjunath Kudlur,
Scott A. Mahlke,
David F. Bacon,
Rodric M. Rabbah:
Optimus: efficient realization of streaming applications on FPGAs.
CASES 2008: 41-50 |
| 91 | | Kevin Fan,
Hyunchul Park,
Manjunath Kudlur,
Scott A. Mahlke:
Modulo scheduling for highly customized datapaths to increase hardware reusability.
CGO 2008: 124-133 |
| 90 | | Ganesh S. Dasika,
Shidhartha Das,
Kevin Fan,
Scott A. Mahlke,
David Bull:
DVFS in loop accelerators using BLADES.
DAC 2008: 894-897 |
| 89 | | Hongtao Zhong,
Mojtaba Mehrara,
Steven A. Lieberman,
Scott A. Mahlke:
Uncovering hidden loop level parallelism in sequential applications.
HPCA 2008: 290-301 |
| 88 | | Nathan Clark,
Amir Hormati,
Scott A. Mahlke:
VEAL: Virtualized Execution Accelerator for Loops.
ISCA 2008: 389-400 |
| 87 | | Shantanu Gupta,
Shuguang Feng,
Amin Ansari,
Jason A. Blome,
Scott A. Mahlke:
The StageNet fabric for constructing resilient multicore systems.
MICRO 2008: 141-151 |
| 86 | | Mark Woh,
Yuan Lin,
Sangwon Seo,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Richard Bruce,
Danny Kershaw,
Alastair Reid,
Mladen Wilder,
Krisztián Flautner:
From SODA to scotch: The evolution of a wireless baseband processor.
MICRO 2008: 152-163 |
| 85 | | Yin Wang,
Terence Kelly,
Manjunath Kudlur,
Stéphane Lafortune,
Scott A. Mahlke:
Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs.
OSDI 2008: 281-294 |
| 84 | | Hyunchul Park,
Kevin Fan,
Scott A. Mahlke,
Taewook Oh,
Heeseok Kim,
Hong-seok Kim:
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.
PACT 2008: 166-176 |
| 83 | | Manjunath Kudlur,
Scott A. Mahlke:
Orchestrating the execution of stream programs on multicore platforms.
PLDI 2008: 114-124 |
| 82 | | Todd M. Austin,
Valeria Bertacco,
Scott A. Mahlke,
Yu Cao:
Reliable Systems on Unreliable Fabrics.
IEEE Design & Test of Computers 25(4): 322-332 (2008) |
| 2007 |
|---|
| 81 | | Yuan Lin,
Manjunath Kudlur,
Scott A. Mahlke,
Trevor N. Mudge:
Hierarchical coarse-grained stream compilation for software defined radio.
CASES 2007: 115-124 |
| 80 | | Amir Hormati,
Nathan Clark,
Scott A. Mahlke:
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping.
CGO 2007: 341-353 |
| 79 | | Nathan Clark,
Amir Hormati,
Sami Yehia,
Scott A. Mahlke,
Krisztián Flautner:
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping.
HPCA 2007: 216-227 |
| 78 | | Hongtao Zhong,
Steven A. Lieberman,
Scott A. Mahlke:
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications.
HPCA 2007: 25-36 |
| 77 | | Michael L. Chu,
Scott A. Mahlke:
Code and data partitioning for fine-grain parallelism.
LCTES 2007: 161-164 |
| 76 | | Rajiv A. Ravindran,
Michael L. Chu,
Scott A. Mahlke:
Compiler-managed partitioned data caches for low power.
LCTES 2007: 237-247 |
| 75 | | Jason A. Blome,
Shuguang Feng,
Shantanu Gupta,
Scott A. Mahlke:
Self-calibrating Online Wearout Detection.
MICRO 2007: 109-122 |
| 74 | | Michael L. Chu,
Rajiv A. Ravindran,
Scott A. Mahlke:
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures.
MICRO 2007: 369-380 |
| 73 | | Mark Woh,
Sangwon Seo,
Hyunseok Lee,
Yuan Lin,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
The Next Generation Challenge for Software Defined Radio.
SAMOS 2007: 343-354 |
| 72 | | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A High-Performance DSP Architecture for Software-Defined Radio.
IEEE Micro 27(1): 114-123 (2007) |
| 71 | | Antonio González,
Scott A. Mahlke,
Shubu Mukherjee,
Resit Sendag,
Derek Chiou,
Joshua J. Yi:
Reliability: Fallacy or Reality?
IEEE Micro 27(6): 36-45 (2007) |
| 70 | | Kypros Constantinides,
Stephen Plaza,
Jason A. Blome,
Valeria Bertacco,
Scott A. Mahlke,
Todd M. Austin,
Bin Zhang,
Michael Orshansky:
Architecting a reliable CMP switch architecture.
TACO 4(1): (2007) |
| 2006 |
|---|
| 69 | | Hyunchul Park,
Kevin Fan,
Manjunath Kudlur,
Scott A. Mahlke:
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.
CASES 2006: 136-146 |
| 68 | | Nathan Clark,
Amir Hormati,
Scott A. Mahlke,
Sami Yehia:
Scalable subgraph mapping for acyclic computation accelerators.
CASES 2006: 147-157 |
| 67 | | Jason A. Blome,
Shantanu Gupta,
Shuguang Feng,
Scott A. Mahlke:
Cost-efficient soft error protection for embedded microprocessors.
CASES 2006: 421-431 |
| 66 | | Michael L. Chu,
Scott A. Mahlke:
Compiler-directed Data Partitioning for Multicluster Processors.
CGO 2006: 208-220 |
| 65 | | Manjunath Kudlur,
Kevin Fan,
Scott A. Mahlke:
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines.
CODES+ISSS 2006: 270-275 |
| 64 | | Kevin Fan,
Manjunath Kudlur,
Hyunchul Park,
Scott A. Mahlke:
Increasing hardware efficiency with multifunction loop accelerators.
CODES+ISSS 2006: 276-281 |
| 63 | | Kypros Constantinides,
Stephen Plaza,
Jason A. Blome,
Bin Zhang,
Valeria Bertacco,
Scott A. Mahlke,
Todd M. Austin,
Michael Orshansky:
BulletProof: a defect-tolerant CMP switch architecture.
HPCA 2006: 5-16 |
| 62 | | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A Low-power Architecture For Software Radio.
ISCA 2006: 89-101 |
| 61 | | Yuan Lin,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Alastair Reid,
Krisztián Flautner:
Design and Implementation of Turbo Decoders for Software Defined Radio.
SiPS 2006: 22-27 |
| 2005 |
|---|
| 60 | | Sami Yehia,
Nathan Clark,
Scott A. Mahlke,
Krisztián Flautner:
Exploring the design space of LUT-based transparent accelerators.
CASES 2005: 11-21 |
| 59 | | Rajiv A. Ravindran,
Pracheeti D. Nagarkar,
Ganesh S. Dasika,
Eric D. Marsman,
Robert M. Senger,
Scott A. Mahlke,
Richard B. Brown:
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.
CGO 2005: 179-190 |
| 58 | | Hyunseok Lee,
Yuan Lin,
Yoav Harel,
Mark Woh,
Scott A. Mahlke,
Trevor N. Mudge,
Krisztián Flautner:
Software Defined Radio - A High Performance Embedded Challenge.
HiPEAC 2005: 6-26 |
| 57 | | Hongtao Zhong,
Kevin Fan,
Scott A. Mahlke,
Michael S. Schlansker:
A Distributed Control Path Architecture for VLIW Processors.
IEEE PACT 2005: 197-206 |
| 56 | | Nathan Clark,
Jason A. Blome,
Michael L. Chu,
Scott A. Mahlke,
Stuart Biles,
Krisztián Flautner:
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors.
ISCA 2005: 272-283 |
| 55 | | Kevin Fan,
Manjunath Kudlur,
Hyunchul Park,
Scott A. Mahlke:
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.
MICRO 2005: 219-232 |
| 54 | | Nathan Clark,
Hongtao Zhong,
Scott A. Mahlke:
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration.
IEEE Trans. Computers 54(10): 1258-1270 (2005) |
| 53 | | Rajiv A. Ravindran,
Robert M. Senger,
Eric D. Marsman,
Ganesh S. Dasika,
Matthew R. Guthaus,
Scott A. Mahlke,
Richard B. Brown:
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers 54(8): 998-1012 (2005) |
| 2004 |
|---|
| 52 |  | Mary Jane Irwin,
Wei Zhao,
Luciano Lavagno,
Scott A. Mahlke:
Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004
ACM 2004 |
| 51 | | Manjunath Kudlur,
Kevin Fan,
Michael L. Chu,
Scott A. Mahlke:
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.
ASAP 2004: 304-314 |
| 50 | | Mikhail Smelyanskiy,
Scott A. Mahlke,
Edward S. Davidson:
Probabilistic Predicate-Aware Modulo Scheduling.
CGO 2004: 151-162 |
| 49 | | Manjunath Kudlur,
Kevin Fan,
Michael L. Chu,
Rajiv A. Ravindran,
Nathan Clark,
Scott A. Mahlke:
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths.
CGO 2004: 201-212 |
| 48 | | Rajeev Krishna,
Scott A. Mahlke,
Todd M. Austin:
Memory system design space exploration for low-power, real-time speech recognition.
CODES+ISSS 2004: 140-145 |
| 47 | | Lakshmi N. Chakrapani,
John C. Gyllenhaal,
Wen-mei W. Hwu,
Scott A. Mahlke,
Krishna V. Palem,
Rodric M. Rabbah:
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism.
LCPC 2004: 32-41 |
| 46 | | Nathan Clark,
Manjunath Kudlur,
Hyunchul Park,
Scott A. Mahlke,
Krisztián Flautner:
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.
MICRO 2004: 30-40 |
| 45 | | Todd M. Austin,
David Blaauw,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Wayne Wolf:
Mobile Supercomputers.
IEEE Computer 37(5): 81-83 (2004) |
| 44 | | Michael L. Chu,
Kevin Fan,
Rajiv A. Ravindran,
Scott A. Mahlke:
Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors.
IEEE Micro 24(3): 10-20 (2004) |
| 2003 |
|---|
| 43 | | Kevin Fan,
Nathan Clark,
Michael L. Chu,
K. V. Manjunath,
Rajiv A. Ravindran,
Mikhail Smelyanskiy,
Scott A. Mahlke:
Systematic Register Bypass Customization for Application-Specific Processors.
ASAP 2003: 64-74 |
| 42 | | Rajiv A. Ravindran,
Robert M. Senger,
Eric D. Marsman,
Ganesh S. Dasika,
Matthew R. Guthaus,
Scott A. Mahlke,
Richard B. Brown:
Increasing the number of effective registers in a low-power processor using a windowed register file.
CASES 2003: 125-136 |
| 41 | | Rajeev Krishna,
Scott A. Mahlke,
Todd M. Austin:
Architectural optimizations for low-power, real-time speech recognition.
CASES 2003: 220-231 |
| 40 | | Mikhail Smelyanskiy,
Scott A. Mahlke,
Edward S. Davidson,
Hsien-Hsin S. Lee:
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints.
CGO 2003: 169-178 |
| 39 | | Nathan Clark,
Hongtao Zhong,
Scott A. Mahlke:
Processor Acceleration Through Automated Instruction Set Customization.
MICRO 2003: 129-140 |
| 38 | | Michael L. Chu,
Kevin Fan,
Scott A. Mahlke:
Region-based hierarchical operation partitioning for multicluster processors.
PLDI 2003: 300-311 |
| 37 | | Nathan Clark,
Hongtao Zhong,
Wilkin Tang,
Scott A. Mahlke:
Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration.
International Journal of Parallel Programming 31(6): 429-449 (2003) |
| 2002 |
|---|
| 36 | | Robert Schreiber,
Shail Aditya,
Scott A. Mahlke,
Vinod Kathail,
B. Ramakrishna Rau,
Darren C. Cronquist,
Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.
VLSI Signal Processing 31(2): 127-142 (2002) |
| 2001 |
|---|
| 35 | | Scott A. Mahlke,
Rajiv A. Ravindran,
Michael S. Schlansker,
Robert Schreiber,
Timothy Sherwood:
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1355-1371 (2001) |
| 2000 |
|---|
| 34 | | Robert Schreiber,
Shail Aditya,
B. Ramakrishna Rau,
Vinod Kathail,
Scott A. Mahlke,
Santosh G. Abraham,
Greg Snider:
High-Level Synthesis of Nonprogrammable Hardware Accelerators.
ASAP 2000: 113- |
| 33 | | Shail Aditya,
Scott A. Mahlke,
B. Ramakrishna Rau:
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.
ACM Trans. Design Autom. Electr. Syst. 5(4): 752-773 (2000) |
| 1999 |
|---|
| 32 | | David I. August,
John W. Sias,
Jean-Michel Puiatti,
Scott A. Mahlke,
Daniel A. Connors,
Kevin M. Crozier,
Wen-mei W. Hwu:
The Program Decision Logic Approach to Predicated Execution.
ISCA 1999: 208-219 |
| 31 | | Santosh G. Abraham,
Scott A. Mahlke:
Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems.
MICRO 1999: 114-125 |
| 30 | | Michael S. Schlansker,
Scott A. Mahlke,
Richard Johnson:
Control CPR: A Branch Height Reduction Optimization for EPIC Architectures.
PLDI 1999: 155-168 |
| 29 | | David I. August,
Wen-mei W. Hwu,
Scott A. Mahlke:
The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication.
International Journal of Parallel Programming 27(5): 381-423 (1999) |
| 1998 |
|---|
| 28 | | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 408-417 |
| 27 | | David I. August,
Daniel A. Connors,
Scott A. Mahlke,
John W. Sias,
Kevin M. Crozier,
Ben-Chung Cheng,
Patrick R. Eaton,
Qudus B. Olaniran,
Wen-mei W. Hwu:
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture.
ISCA 1998: 227-237 |
| 1997 |
|---|
| 26 | | David I. August,
Wen-mei W. Hwu,
Scott A. Mahlke:
A Framework for Balancing Control Flow and Predication.
MICRO 1997: 92-103 |
| 1996 |
|---|
| 25 | | Scott A. Mahlke,
Balas K. Natarajan:
Compiler Synthesized Dynamic Branch Prediction.
MICRO 1996: 153-164 |
| 1995 |
|---|
| 24 | | Roger A. Bringmann,
Scott A. Mahlke,
Wen-mei W. Hwu:
A study of the effects of compiler-controlled speculation on instruction and data caches.
HICSS (1) 1995: 211-220 |
| 23 | | Scott A. Mahlke,
Richard E. Hank,
James E. McCormick,
David I. August,
Wen-mei W. Hwu:
A Comparison of Full and Partial Predicated Execution Support for ILP Processors.
ISCA 1995: 138-150 |
| 22 | | Pohua P. Chang,
Daniel M. Lavery,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.
IEEE Trans. Computers 44(3): 353-370 (1995) |
| 21 | | Pohua P. Chang,
Nancy J. Warter,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
Three Architecutral Models for Compiler-Controlled Speculative Execution.
IEEE Trans. Computers 44(4): 481-494 (1995) |
| 1994 |
|---|
| 20 | | David M. Gallagher,
William Y. Chen,
Scott A. Mahlke,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Dynamic Memory Disambiguation Using the Memory Conflict Buffer.
ASPLOS 1994: 183-193 |
| 19 | | Scott A. Mahlke,
Richard E. Hank,
Roger A. Bringmann,
John C. Gyllenhaal,
David M. Gallagher,
Wen-mei W. Hwu:
Characterizing the impact of predicated execution on branch prediction.
MICRO 1994: 217-227 |
| 1993 |
|---|
| 18 | | Tokuzo Kiyohara,
Scott A. Mahlke,
William Y. Chen,
Roger A. Bringmann,
Richard E. Hank,
Sadun Anik,
Wen-mei W. Hwu:
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures.
ISCA 1993: 247-256 |
| 17 | | Roger A. Bringmann,
Scott A. Mahlke,
Richard E. Hank,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Speculative execution exception recovery using write-back suppression.
MICRO 1993: 214-223 |
| 16 | | Richard E. Hank,
Scott A. Mahlke,
Roger A. Bringmann,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Superblock formation using static program analysis.
MICRO 1993: 247-255 |
| 15 | | Nancy J. Warter,
Scott A. Mahlke,
Wen-mei W. Hwu,
B. Ramakrishna Rau:
Reverse If-Conversion.
PLDI 1993: 290-299 |
| 14 | | Scott A. Mahlke,
William Y. Chen,
Roger A. Bringmann,
Richard E. Hank,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ACM Trans. Comput. Syst. 11(4): 376-408 (1993) |
| 1992 |
|---|
| 13 | | Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ASPLOS 1992: 238-247 |
| 12 | | William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu:
Tolerating First Level Memory Access Latency in High-Performance Systems.
ICPP (1) 1992: 36-43 |
| 11 | | William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu,
Tokuzo Kiyohara,
Pohua P. Chang:
Tolerating data access latency with register preloading.
ICS 1992: 104-113 |
| 10 | | William Y. Chen,
Roger A. Bringmann,
Scott A. Mahlke,
Sadun Anik,
Tokuzo Kiyohara,
Nancy J. Warter,
Daniel M. Lavery,
Wen-mei W. Hwu,
Richard E. Hank,
John C. Gyllenhaal:
Using Profile Information to Assist Advaced Compiler Optimization and Scheduling.
LCPC 1992: 31-48 |
| 9 | | Scott A. Mahlke,
David C. Lin,
William Y. Chen,
Richard E. Hank,
Roger A. Bringmann:
Effective compiler support for predicated execution using the hyperblock.
MICRO 1992: 45-54 |
| 8 | | William Y. Chen,
Roger A. Bringmann,
Scott A. Mahlke,
Richard E. Hank,
James E. Sicolo:
An efficient architecture for loop based data preloading.
MICRO 1992: 92-101 |
| 7 | | Scott A. Mahlke,
William Y. Chen,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Compiler Code Transformations for Superscalar-Based High Performance Systems.
SC 1992: 808-817 |
| 6 | | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
Profile-guided Automatic Inline Expansion for C Programs.
Softw., Pract. Exper. 22(5): 349-369 (1992) |
| 1991 |
|---|
| 5 | | Scott A. Mahlke,
Nancy J. Warter,
William Y. Chen,
Pohua P. Chang,
Wen-mei W. Hwu:
The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs.
ICPP (2) 1991: 142-145 |
| 4 | | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
ISCA 1991: 266-275 |
| 3 | | Pohua P. Chang,
William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.
MICRO 1991: 25-33 |
| 2 | | William Y. Chen,
Scott A. Mahlke,
Pohua P. Chang,
Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.
MICRO 1991: 69-73 |
| 1 | | Pohua P. Chang,
Scott A. Mahlke,
Wen-mei W. Hwu:
Using Profile Information to Assist Classic Code Optimizations.
Softw., Pract. Exper. 21(12): 1301-1321 (1991) |
